An edge-triggered, clocked storage unit that stores a single bit of data. A low-to-high transition on the clock signal changes the output of the flipflop, based on the value of the data input(s). This value is maintained until the next low-to-high transition of the clock, or until the flipflop is preset or cleared.

Depending on the architecture of the device family, a register can be programmed as a level-sensitive flow-through latch or as an edge-triggered D, T, JK, or SR flipflop.

In Verilog HDL, "register" (or "reg") is also used to describe the abstraction of a data storage device. When this register is used in an Always Construct that is sensitive to the rising or falling edge of a Clock, the Quartus^® II Compiler translates that register into a flipflop. Verilog HDL registers can be scalar or vector.

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