A basic building block in APEX^™ 20K, APEX^™ II, ARM^®-based Excalibur^™, MAX^® 3000, and MAX 7000 devices. A macrocell is also generally known as a logic cell.

In APEX 20K, APEX II, and ARM-based Excalibur devices, a macrocell is a basic building block of an Embedded System Block (ESB) that is set to use product-term mode. Each macrocell consists of two product terms and a programmable register, and can be configured individually for either sequential or combinatorial logic operation. A macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register.

The product-term select matrix of an APEX 20K, APEX II, or ARM-based Excalibur macrocell allocates product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as parallel expanders to increase the logic available to another macrocell. The Quartus^® II software can invert one product term to perform DeMorgan's inversion for more efficient implementation of wide OR functions. The Quartus II Compiler can also use the NOT Gate Push-Back logic option to emulate an asynchronous preset.

Each programmable register of an APEX 20K, APEX II, or ARM-based Excalibur macrocell can be programmed individually to implement D, T, JK, or SR operation with programmable clock control; or bypassed entirely for combinatorial operation. During design entry, you specify the desired register type; the Quartus II software then selects the most efficient register operation for each registered function to optimize resource utilization. The Quartus II software or other synthesis tools can also select the most efficient register operation automatically when synthesizing HDL designs.

The programmable register can be clocked by one of two ESB-wide clocks. The ESB-wide clocks can be generated from device dedicated clock pins, global signals, or the local interconnect. Each clock also has an associated clock enable, generated from the local interconnect. The clock and clock enable signals are related for a particular ESB; any macrocell using a clock also uses the associated clock enable.

In MAX 3000 and MAX 7000 devices, a macrocell is a basic building block that consists of five product terms and a configurable register, and can be configured individually for either sequential or combinatorial logic operation. A macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register.

The product–term select matrix of a MAX 3000 or MAX 7000 macrocell allocates product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocell’s register preset, clock, and clock enable control functions.

Each programmable register of a MAX 3000 or MAX 7000 macrocell can be programmed individually to implement D, T, JK, or SR operation with programmable clock control; or bypassed entirely for combinatorial operation. During design entry, you specify the desired register type; the Quartus II software then selects the most efficient register operation for each registered function to optimize resource utilization. The Quartus II software or other synthesis tools can also select the most efficient register operation automatically when synthesizing HDL designs.

The programmable register can be clocked by one of the following clocks:

• A global clock.

• A global clock enabled by an active-high clock enable that is generated by a product term.

• An array clock that is implemented with a product term.

MAX 3000 and MAX 7000 devices contain two global clocks, each of which can be the true or the complement of one of the two global clock pins, GCLK1 or GCLK2.

The programmable register also supports asynchronous preset and clear functions. The product–term select matrix allocates product terms to control these operations. Although the preset and clear from the register are active-high, you can use the signals as active–low by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active–low dedicated global clear (GCLRn).

Macrocells have "numbers" of the following format:

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