Primitive

CARRY_SUM Primitive



AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION CARRY_SUM (sin, cin)
   RETURNS (sout, cout)


VHDL Component Declaration:

COMPONENT CARRY_SUM
   PORT (sin, cin : IN STD_LOGIC;
   sout, cout : OUT STD_LOGIC;);
END COMPONENT;

The CARRY_SUM primitive is a two-input, two-output primitive that designates the carry-out and sum-out logic for a function. The cout port of the primitive acts as the carry-in for the next element of the carry chain. The carry function implements fast carry-chain logic for functions such as adders and counters.

When you use a CARRY_SUM primitive, you must observe the following rules:

You can direct the Compiler to automatically insert CARRY_SUM primitives during logic synthesis with the Auto Carry Chains logic option.

NOTE The CARRY_SUM primitive is not supported for MAX® 3000 or MAX 7000 devices.


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