Megafunctions

altpll_reconfig (Phase-Locked Loop Reconfiguration) Megafunction

Parameterized phase-locked loop (PLL) reconfiguration megafunction. The altpll_reconfig megafunction enables real-time control of the PLL. The altmemmult megafunction is available for Cyclone™, Stratix™, and Stratix™ GX devices only.

Altera® recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

This topic contains the following information:


AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION altpll_reconfig (clock, reset, data_in[8..0], counter_type[3..0], counter_param[2..0], read_param,
      write_param, reconfig, pll_scandataout )
   WITH (SCAN_CHAIN, SCAN_INIT_FILE )
   RETURNS (data_out[8..0], busy, pll_scanclk, pll_scanaclr, pll_scandata );


VHDL Component Declaration:

 
COMPONENT altpll_reconfig
   GENERIC 
      (SCAN_CHAIN     : STRING;
      SCAN_INIT_FILE  : STRING := "UNUSED");

   PORT (clock, reset                                       : IN STD_LOGIC;
        data_in                                             : IN STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0');
        counter_type                                        : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
        counter_param                                       : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
        read_param, write_param, reconfig, pll_scandataout  : IN STD_LOGIC                    := '0';
        busy, pll_scanclk, pll_scanaclr, pll_scandata       : OUT STD_LOGIC;
        data_out                                            : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);

END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;


Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
clock Yes Clock input port that drives this megafunction during reconfiguration. The clock input port must be connected to a valid clock.
reset Yes Asynchronous reset input to this megafunction.  
data_in[] No Data input that provides parameter value when writing parameters. Input port [8 DOWNTO 0] wide.
counter_type[] No Specifies the counter type. Input port [3 DOWNTO 0] wide. Defaults to 0. Use the following mapping settings:

Value Counter Type
0 N
1 M
2 --
3 --
4 a0
5 a1
6 a2
7 a3
8 l0
9 l1
10 --
11 --
12 e0
13 e1
14 e2
15 e3

counter_param[] No Specifies the parameter for the value specified in the counter_type port. Input port [2 DOWNTO 0] wide. Defaults to 0. Use the following mapping settings:

Value Selected Parameter Width
0 "nominal count" (for M, N) 9
1 "spread count" (for M, N) 9
2 "high cycles count" (for G, L, E) 9
3 "low cycles count" (for G, L, E) 9
4 "delay element setting" 4
5 -- --
6 "counter bypass bit" 1
7 "counter odd division bit" (must be 0 for M, N) 1
8 -- --
9 -- --

read_param No Reads the parameter specified with the counter_type and counter_param port from the cache and fed to dataout port. Should only be asserted for one clock cycle to prevent multiple reads. The busy port indicates when the read is complete.
write_param xx_Yes_or_No_xx Writes the parameter specified with the counter_type and counter_param port to the cache with the value specified in the data_in port. Should only be asserted for one clock cycle to prevent multiple reads. The busy port indicates when the read is complete.
reconfig Yes Specifies that the PLL should be reconfigured with the PLL settings specified in the current cache. Should only be asserted for one clock cycle to prevent multiple reads. The busy port indicates when the read is complete.
pll_scandataout Yes Signal driven by the PLL to be reconfigured. The pll_scandataout port must be connected to the PLL's scandataout port.

OUTPUT PORTS

Port Name Required Description Comments
data_out[] No Data read from the cache when read_param is asserted. Output port [8 DOWNTO 0] wide.
busy No Busy signal that indicates when the PLL is reading or writing a parameter to the cache, or configuring the PLL. While busy is asserted, not parameters can be read or written, and no reconfiguration can be initiated.
pll_scanclk Yes Drives the scanclk port on the PLL that will be reconfigured.  
pll_scanaclr Yes Drives the scanaclr port on the PLL that will be reconfigured.  
pll_scandata Yes Drives the scandata port on the PLL that will be reconfigured.  


Parameter Descriptions:
Parameter Type Required Comments
SCAN_CHAIN String Yes Specifies the type of scan chain. Values are "LONG" or "SHORT".

Value Configuration Setting
LONG 288-bit scan chain used to control PLLs with 12 counters.
SHORT 192-bit scan chain used to control PLLs with 8 counters.

SCAN_INIT_FILE String No Specifies the name of the Memory Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex) used as the initial value of the scan chain cache. If omitted, the scan chain is initialized with an unknown state.

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