See Also

LogicLock^™ back-annotation allows you to back-annotate one or more LogicLock regions in your design. When you back-annotate a LogicLock region, the Quartus^® II software automatically back-annotates all of the region's descendant LogicLock regions. You can choose to back-annotate LogicLock region size and location only, or contents as well.

Back-annotating a LogicLock region's size and location sets the region's height, width, and origin to the values determined by the Fitter during the last compilation and locks the region at this origin.

Back-annotating a LogicLock region's contents back-annotates the region's size and location and also the placement of nodes and entities assigned to the region. When you back-annotate a LogicLock region's contents, the Quartus II software copies the locations determined by the Fitter for all nodes and entities assigned to the region into the Entity Settings File (.esf) for the top-level entity in the current compilation hierarchy. Nodes are back-annotated relative to the origin of the LogicLock region to which they are assigned. If you move the region, the Quartus II software updates the node locations to preserve the relative placement of nodes and entities within the region. If you unlock the region, the Compiler is free to place the region at a new location but preserves the relative placement of nodes and entities within the region.

Before back-annotating either the size and location or the contents of a descendant LogicLock region, you should back-annotate the size and location of its top-level ancestor LogicLock region. Otherwise, back-annotation may create illegal LogicLock region assignments (for example, a child region that exceeds the bounds of its parent region).

LogicLock node back-annotation demotes cell assignments to the LAB/Embedded System Block (ESB) level. Demoting cell assignments to less restrictive LAB or ESB assignments allows the Compiler to rearrange nodes within a LAB or ESB for greatest efficiency.

The Current Assignments Floorplan and Timing Closure floorplan outline LABs and ESBs containing LogicLock node back-annotation.

You can back-annotate only the width, height and origin of a LogicLock region from last compilation by turning on Region write-back in the Back-Annotate Assignments dialog box.

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