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To use the Synopsys® VHDL System Simulator (VSS) software to perform a functional simulation of a VHDL design that contains Altera-specific components:
If you have not already done so, perform 1. Set Up the VSS Working Environment.
Add the following lines to your .synopsys_vss.setup file to include the mapping information for the work library, and to direct the VSS software to use the functional simulation libraries during simulation:
WORK >
<work library>
220model >
<work library>
altera_mf >
<work library>
<work library> >
<physical path to work library>
Add the altera variable if you wish to to simulate the architecture control logic functions in the alt_mf library, located at /usr/quartus/eda/synopsys/library/alt_mf/lib. |
Create a work library in the project directory by typing the following command at a command prompt: More Details
mkdir
<work library>
To compile the VHDL Design File (.vhd), test bench file (if you are using one) and Altera® prerouting simulation libraries, type the following commands at a command prompt:
vhdlan
<test bench file>
vhdlan
<design name>.vhd
vhdlan
/usr/quartus/eda/sim_lib/220model.vhd
vhdlan
/usr/quartus/eda/sim_lib/altera_mf.vhd
For VHDL 87-compliant designs, type the following commands to compile the VHDL-87 compliant simulation model libraries:
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To simulate the design, type the following command at a command prompt (where <VHDL configuration name> represents the configuration name in the test bench file):
scsim
<work library>.
<VHDL configuration name>
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To continue with the VSS simulation flow, proceed to 3. Perform a Timing Simulation with the VSS Software.
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