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To use the Cadence Verilog-XL software to perform a functional simulation of a Verilog HDL design that contains Altera-specific components:

1. If you have not already done so, perform 1. Set Up the Verilog-XL Working Environment.

2. If your design contains content-addressable memory (CAM), RAM, or ROM functions, and you are using a Hexadecimal (Intel-Format) File (.hex), to convert the HEX File:

1. Export the Hexadecimal (Intel-Format) File (.hex) as a RAM Initialization File (.rif) in the Quartus^® II software.

2. Add parameter lpm_file = "<RIF name>.rif"; for the CAM, RAM, or ROM function to your top-level design or test bench file.

3. Type the following commands to compile the 220model.v and altera_mf.v simulation libraries:

   vlog +define+NO_PLI 220model.v 
vlog +define+NO_PLI altera_mf.v 

3. If your design has CAM, RAM, or ROM functions, to start the Verilog-XL software and simulate your Verilog design file and test bench file (if you are using one), type the following command at the command prompt:

   verilog <test bench>.v <design name>.vo +define+NO_PLI /quartus/eda/sim_lib/altera_mf.v +define+NO_PLI /quartus/eda/sim_lib/220model.v 

4. If you are not using CAM, RAM, or ROM functions, to start the Verilog-XL software and simulate your Verilog design file and test bench file, type the following command at the command prompt:

   verilog <test bench> <design name>.vo /quartus/eda/sim_lib/altera_mf.v /quartus/eda/sim_lib/220model.v 

If your design contains the altgxb megafunction, you must also specify the stratixgx_mf.v functional simulation library, located in the \quartus\eda\sim_lib\verilog_xl\ directory. You must also set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

5. Refer to the VCS User Guide for more information on the required and optional environment variables.

6. To continue with the Verilog-XL simulation flow, proceed to 3. Perform a Timing Simulation with the Verilog-XL Software.

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