Overviews

Commands

See Also

To use the Synopsys^® Scirocco software to perform a functional simulation of a VHDL design that contains Altera-specific components:

1. If you have not already done so, perform 1. Set Up the Scirocco Working Environment.

2. Add the following lines to your .synopsys_vss.setup file to include the mapping information for the work library, and to direct the Scirocco software to use the functional simulation libraries during simulation:

   WORK > <work library>
   220model > <work library>
   altera_mf > <work library>
   <work library> > <physical path to work library>

3. If your design contains the altgxb megafunction, add the following lines to your .synopsys_vss.setup file to map to the precompiled Stratix^™ GX functional simulation model libraries:

altgxb > <alias name>
<alias name> : /quartus/eda/sim_lib/scirocco/altgxb

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

4. Create a work library in the project directory by typing the following command at a command prompt: More Details

mkdir <work library> 

5. Create a work library in the project directory by typing the following command at a command prompt:  More Details

mkdir <work library> 

6. To compile the VHDL Design File (.vhd), test bench file (if you are using one) and Altera^® prerouting simulation libraries, type the following commands at a command prompt:

vhdlan <test bench file> 
vhdlan <design name>.vhd 
vhdlan /usr/quartus/eda/sim_lib/220model.vhd 
vhdlan /usr/quartus/eda/sim_lib/altera_mf.vhd 


For VHDL 87-compliant designs, type the following commands to compile the VHDL-87 compliant simulation model libraries: vhdlan -vhdl87 /usr/quartus/eda/sim_lib/220model_87.vhd  vhdlan -vhdl87 /usr/quartus/eda/sim_lib/altera_mf_87.vhd

7. To simulate the design, type the following command at a command prompt (where <VHDL configuration name> represents the configuration name in the test bench file):

scsim <work library>.<VHDL configuration name> 

The Scirocco software requires each architecture or entity pair in a VHDL Design File to have a configuration. The Configuration Declaration is necessary for simulation, but not for synthesis.

8. To view the results of the simulation, type virsim  at the command prompt to launch the Scirocco interface.

9. To continue with the Scirocco simulation flow, proceed to 3. Perform a Timing Simulation with the Scirocco Software.

Back to Top