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Setting up a project in the FPGA Compiler II software includes starting the software, adding Verilog HDL and VHDL design files to the project, and selecting a device and clock frequency for the project. You can specify the desired clock frequency (called f_MAX in the Quartus^® II software) and the target device family before synthesizing and optimizing the design. You can optionally select a specific device and speed grade within the target device family. These assignments are stored in the design's Assignment & Configuration File, <design name>.acf, which is generated automatically by the FPGA Compiler II software.

To set up a project with the FPGA Compiler II software:

1. If you have not already done so, perform 2. Create a Design for Use with the FPGA Compiler II Software.

2. Start the FPGA Compiler II software. Choose New Project (File menu).

3. Specify the full file and path name of your project in the Create New FPGA Compiler II Project dialog box and click Create. The FPGA Compiler II software creates the project and opens the Add Sources dialog box.

4. To identify and analyze the source file for the project (that is, the top-level design entity file that contains the "black box" for the file created by the MegaWizard^® Plug-In Manager) select them in the Add Sources dialog box and click Open. You should not analyze the MegaWizard-generated file directly in the FPGA Compiler II software, but you should add these files to the project instead. The FPGA Compiler II internal analyzer automatically analyzes each source file as it appears on the left side of the Project window. A green check mark appears to the left of each filename for the files that have no errors or warnings, a red "x" appears for files with errors, and an exclamation point appears for files with warnings.

5. Select the source file icon to display any errors or warnings in the Output window. To locate the source of an error, double-click the error. The FPGA Compiler II internal text editor automatically displays the source file and highlights the line containing the error or warning in red. To view help on the error or warning, double-click the error or warning code number (shown in parentheses) in the Output window.

   FPGA Compiler II software does not copy source files; it identifies and analyzes them in their current location. Refer to FPGA Compiler II Help for more information.

6. To assign a device or device family and the clock frequency:

1. If you have not already done so, identify the top-level design for your project from the Design Sources window. Select the top-level design from the Identify top-level design list on the toolbar. The Create Implementation dialog box appears.
2. Enter an implementation name in the Implementation Name box. If you do not enter a name, FPGA Compiler II software automatically creates a unique implementation name.

3. Under Target device, specify the following options:

1. In the Vendor list, select Altera^®.
2. In the Family list, select the appropriate Altera device family.
3. In the Device list, select a specific device, and select a specific speed grade from the Speed grade list. If you choose AUTO in the Device list, the speed grade is set to FASTEST.

4. In the Clock frequency box, type the desired clock frequency. The clock frequency is used as the default value for all clock signals in the design.

The FPGA Compiler II software processes each source file and determines the complete hierarchical structure and topology of the design, including multi-level links and references between subdesigns. With this information, the FPGA Compiler II software produces an intermediate, unoptimized design implementation. The right side of the Project window displays the implementation name and target device. The implementation icon also indicates any errors, warnings, or other information. To locate the source of errors or warnings, double-click the error or warning.

7. To continue with the FPGA Compiler II design flow, proceed to 4. Assign Constraints and Optimize the Design with the FPGA Compiler II Software.

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