EDA Interfaces

Example of Creating a Verilog HDL Custom Variation of the altclklock Function

The following example procedure illustrates how to use the MegaWizard® Plug-In Manager to create a custom megafunction variation of the altclklock function. You can follow similar steps to create custom megafunction variations of other megafunctions. To create a custom megafunction variation for the altclklock function:

  1. Choose MegaWizard Plug-In Manager (Tools menu).

  2. In the MegaWizard Plug-In Manager, when you are asked Which action do you want to perform?, select Create a new custom megafunction variation and click Next.

  3. When you are asked Which type of output file do you want to create?, select Verilog HDL.

  4. In the Available Megafunctions list, click on the + icon to expand the I/O folder and select ALTCLKLOCK.

  5. When you are asked What name do you want for the file?, type the appropriate file name or click Browse (...) to select the appropriate location. For this example, the path and file name should be C:\synplify_e_features\verilog\pll\my_pll.v.

  6. Click Next.

  7. To select the device family to which your function should be targeted and to specify related options:

    1. For this example, select APEX™ 20KE when you are asked Use which device family?.

    2. Under Which optional ports are needed?, turn on locked and inclocken.

    3. Under How should the PLL output(s) be generated?, turn on Use the feedback path inside the PLL and specify a value of 0 degrees for with a programmed phase shift of.

    4. Under Place a higher priority on matching the phase shift of, select The external clock [Normal Mode].

  8. Click Next.

    9. NOTE The remaining options are family dependent. The MegaWizard Plug-In Manager guides you to choose valid options for the selected device family.

  9. To specify the input clock frequency and the clock output multiplication and division factors:

    1. When you are asked What is the input clock frequency?, select 40.0 MHz.

    2. When you are asked Which output clocks would you like to use?, select Clock0 and Clock1, using the following clock multiplication and division factors:

      3. Option:Clock0Clock1
      Clock multiplication factor42
      Clock division factor11

  10. Click Next.

  11. To specify the number of cycles to achieve lock and to lose lock:

    1. When you are asked How many synchronized clock cycles should pass before PLL is considered locked?, select 2.5 clock cycles.

    2. When you are asked How many unsynchronized clock cycles should pass before PLL is considered to have lost its lock?, select 2.5 clock cycles.

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  12. Click Next.

  13. The Summary page informs you of the files that the MegaWizard Plug-In Manager will create. In this example, it generates the following files:

    14. C:\synplify_e_features\verilog\pll\my_pll.v
    C:\synplify_e_features\verilog\pll\my_pll.inc
    C:\synplify_e_features\verilog\pll\my_pll.cmp
    C:\synplify_e_features\verilog\pll\my_pll.bsf
    C:\synplify_e_features\verilog\pll\my_pll_bb.v

    For a sample output of the resulting design file, see Example of a Verilog HDL Custom Megafunction Variation of the altclklock Function.

  14. To close the MegaWizard Plug-In Manager, click Finish.


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