See Also

The following sample shows the my_pll.v file, which can be generated from the MegaWizard^® Plug-In Manager, as described in Example of Creating a Verilog HDL Custom Variation of the altclklock Function. The my_pll.v file contains an instantiation and parameters of the altclklock function.

// megafunction wizard: %ALTCLKLOCK%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altclklock 
// ============================================================
// File Name: my_pll.v
// Megafunction Name(s):
// 			altclklock
// ============================================================
// ************************************************************
// THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************

module my_pll (
	inclock,
	inclocken,
	locked,
	clock0,
	clock1);

	input	  inclock;
	input	  inclocken;
	output	  locked;
	output	  clock0;
	output	  clock1;

	wire  sub_wire0;
	wire  sub_wire1;
	wire  sub_wire2;
	wire  clock0 = sub_wire0;
	wire  clock1 = sub_wire1;
	wire  locked = sub_wire2;

	altclklock	altclklock_component (
				.inclocken (inclocken),
				.inclock (inclock),
				.clock0 (sub_wire0),
				.clock1 (sub_wire1),
				.locked (sub_wire2));
	defparam
		altclklock_component.inclock_period = 25000,
		altclklock_component.clock0_boost = 4,
		altclklock_component.clock1_boost = 2,
		altclklock_component.operation_mode = "NORMAL",
		altclklock_component.intended_device_family = "APEX™20KE",
		altclklock_component.valid_lock_cycles = 5,
		altclklock_component.invalid_lock_cycles = 5,
		altclklock_component.valid_lock_multiplier = 5,
		altclklock_component.invalid_lock_multiplier = 5,
		altclklock_component.clock0_divide = 1,
		altclklock_component.clock1_divide = 1,
		altclklock_component.outclock_phase_shift = 0;
endmodule

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