See Also

To specify that the Synplicity Synplify software should treat the my_pll.v file that you created in Example of Creating a Verilog HDL Custom Variation of the altclklock Function as a "black box," refer to the following code sample from the top-level design file. In this example, the top-level design file is pllsource.v. To modify the source code for the pllsource.v file to define the module name and port type and to specify that the module is a black box, you can use the my_pll_bb.v empty module declaration and add it to the pll_source.v top-level design file as shown in the following code sample:

module my_pll (
	inclock,
	inclocken,
	locked,
	clock0,
	clock1 /*synthesis syn_black_box*/ ); 

	input	  inclock;
	input	  inclocken;
	output	  locked;
	output	  clock0;
	output	  clock1;
endmodule

module pllsource (inclock, inclocken, data_in1, clock0, r_out, locked, div2);
	input inclock, inclocken;
	input [7:0] data_in1;
	output clock0, locked;
	output div2;
	output [7:0] r_out;
	
wire clock1_sig;
reg div2;
reg [7:0] r_out, r_int;

my_pll PLL_1
	( .inclock(inclock), .inclocken(inclocken), .clock0(clock0),
	  .clock1(clock1_sig), .locked(locked));

always @(posedge clock1_sig)
begin
	r_int <= data_in1;
	r_out <= r_int;
end

endmodule

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