Overviews

Commands

See Also

To use the Model Technology^™ ModelSim^® PE or SE (non-OEM) software to perform a functional simulation of a VHDL or Verilog HDL design that contains Altera-specific components using command-line commands: Read This First

1. If you have not already done so, perform 2. Set Up a Project with the ModelSim Software (Command-Line).

2. If your design contains the altgxb megafunction, to map to the precompiled Stratix^™ GX functional simulation model libraries type the following command at the ModelSim prompt:

   vmap altgxb \quartus\eda\sim_lib\modelsim\<verilog or vhdl>\altgxb\ 
   

   If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

3. To compile the functional simulation libraries, VHDL or Verilog HDL design file, and optional test bench file, type the following commands at the ModelSim prompt:

   If you are performing a functional simulation of an ARM®-based Excalibur™ design, also compile the appropriate ARM-based Excalibur simulation model wrapper file.

   For VHDL 87-compliant designs:

   vcom [-87] -explicit -work work <path to library>\220model_87.vhd 
vcom -work work <path to library>\220pack.vhd 
vcom -work work <path to library>\altera_mf_components.vhd 
vcom [-87] -work work <path to library>\altera_mf_87.vhd 
vcom -work work <design name>.vhd 
vcom -work work <test bench>.vhd 

   For VHDL 93-compliant designs:

   vcom -explicit -work work <path to library>\220model.vhd 
vcom -93 -work work <path to library>\220pack.vhd 
vcom -work work <path to library>\altera_mf_components.vhd 
vcom -93 -work work <path to library>\altera_mf.vhd 
vcom -work work <design name>.vhd 
vcom -work work <test bench>.vhd 

   For Verilog HDL designs:

   vlog -work work <path to library>\220model.v 
vlog -work work <path to library>\altera_mf.v 
vlog -work work <design name>.v 
vlog -work work <test bench>.v 

4. Load the VHDL or Verilog HDL design file or test bench file for the design into the ModelSim software by typing one of the following commands at the command prompt:

   vsim <work library>.<design name> 

   or

   vsim <work library>.<top-level design entity> 

5. Perform the functional simulation in the ModelSim software.

If you are simulating an ARM-based Excalibur design, the bus functional model generates the output.dat bus functional model simulation file. Refer to ModelSim software documentation for more information on how to view and interpret the results of the simulation.

6. To continue with the ModelSim simulation flow, return to one of the following steps:

   • 2. Set Up a Project with the ModelSim Software
   • 2. Set Up a Project with the ModelSim Software (Command-Line)

Back to Top