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The EM7064B, a member of the MAX® 7000 device family, is based on second-generation MAX architecture and provides 128 registers, and 1,250 usable gates. The EPM7064B meets the low power and voltage requirements of 3.3-V applications ranging from notebook computers to battery-operated, hand-held equipment.
EPM7064B devices are available in 44-pin TQFP packages with 32 I/O pins, 49-pin Ultra Fineline BGA packages with 37 I/O pins, and 100-pin TQFP packages with 64 I/O pins. Each device also contains four dedicated inputs.
The EPM7064B has 64 macrocells divided into 4 LABs. Each macrocell consists of a logic array, a product-term select matrix, and a programmable register. Each macrocell in a LAB can be supplemented with up to 16 shareable expander product terms and 15 high–speed parallel expander product terms to provide up to 32 product terms per macrocell for building complex logic functions. The EPM7032B also supports in-system programmability (ISP) and JTAG BST. The EPM7064B JTAG Instruction Register length is 10 and the JTAG ID code is 270640DD.
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Preliminary support for new device packages may be available for this device. Pin-outs for devices with preliminary support are subject to change. For information on preliminary device support, refer to Quartus® II Software Release Notes, available on the Altera® web site. For complete information on the EPM7064B device, refer to the current MAX 7000B Programmable Logic Device Family Data Sheet, which is available from the Literature section of the Altera web site. |
The following table displays the pin-out information for EPM7064B devices:
Function Config. LCell OE MUX LAB IO TQFP UFBGA TQFP
Pin Pin;LCell Bank 44 49 100
Note (10)
Input/GCLK - - -/- - - 37 A5 87
Input/OE1n - - 1/- - - 38 A4 88
Input/GCLRn - - -/- - - 39 A3 89
Input/OE2n/GCLK - - 3/- - - 40 B4 90
I/O or Buried - 1 -/2 A 1 6 D2 14
I/O or Buried - 2 -/- A 1 - - 13
I/O or Buried VREFA 3 1/2 A 1 5 D1 12
I/O or Buried - 3 1/2 A 1 - - -
I/O or Buried - 4 -/3 A 1 3 D4 10
I/O or Buried - 5 6/4 A 1 2 C1 9
I/O or Buried - 6 -/- A 1 - - 8
I/O or Buried - 7 -/- A 1 - - 6
I/O or Buried TDI 8 -/- A 1 1 B1 4
I/O or Buried - 9 -/- A 1 - B2 100
I/O or Buried - 10 -/- A 1 - - 99
I/O or Buried - 11 3/1 A 1 44 A1 98
I/O or Buried - 12 -/- A 1 - - 97
I/O or Buried - 13 -/- A 1 - - 96
I/O or Buried - 14 5/- A 1 43 A2 94
I/O or Buried - 15 -/- A 1 - - 93
I/O or Buried - 16 4/- A 1 42 C3 92
I/O or Buried - 17 6/5 B 1 15 G4 37
I/O or Buried - 18 -/- B 1 - E3 36
I/O or Buried - 19 6/4 B 1 14 G3 35
I/O or Buried - 20 -/5 B 1 13 F3 33
Function Config. LCell OE MUX LAB IO TQFP UFBGA TQFP
Pin Pin;LCell Bank 44 49 100
Note (10)
I/O or Buried - 21 -/2 B 1 12 G2 32
I/O or Buried - 22 -/- B 1 - G1 31
I/O or Buried - 23 -/- B 1 - - 30
I/O or Buried - 24 1/3 B 1 11 F2 29
I/O or Buried - 25 5/6 B 1 10 D3 25
I/O or Buried - 26 -/- B 1 - - 23
I/O or Buried - 27 -/- B 1 - - 21
I/O or Buried - 28 -/- B 1 - - 20
I/O or Buried - 29 -/- B 1 - - 19
I/O or Buried - 30 3/1 B 1 8 E1 17
I/O or Buried - 31 -/- B 1 - - 16
I/O or Buried VREFA 31 -/- B 1 - - -
I/O or Buried TMS 32 -/- B 1 7 F1 15
I/O or Buried - 33 -/5 C 2 18 E5 40
I/O or Buried - 34 -/- C 2 - - 41
I/O or Buried - 35 6/4 C 2 19 G5 42
I/O or Buried - 36 -/5 C 2 20 F5 44
I/O or Buried - 37 -/- C 2 21 G6 45
I/O or Buried - 38 -/- C 2 - - 46
I/O or Buried - 39 -/- C 2 - G7 47
I/O or Buried - 40 1/3 C 2 22 F6 48
I/O or Buried - 41 5/6 C 2 23 D5 52
I/O or Buried - 42 -/- C 2 - - 54
I/O or Buried - 43 -/- C 2 - - 56
I/O or Buried - 44 -/- C 2 - - 57
Function Config. LCell OE MUX LAB IO TQFP UFBGA TQFP
Pin Pin;LCell Bank 44 49 100
Note (10)
I/O or Buried - 45 -/- C 2 - - 58
I/O or Buried VREFB 46 2/1 C 2 25 E7 60
I/O or Buried - 46 2/1 C 2 - - -
I/O or Buried - 47 -/- C 2 - - 61
I/O or Buried TCK 48 -/- C 2 26 F7 62
I/O or Buried - 49 -/2 D 2 27 D7 63
I/O or Buried - 50 -/- D 2 - - 64
I/O or Buried - 51 1/2 D 2 28 D6 65
I/O or Buried - 52 -/3 D 2 30 C7 67
I/O or Buried VREFB 52 -/3 D 2 - - -
I/O or Buried - 53 6/4 D 2 31 B6 68
I/O or Buried - 54 -/- D 2 - - 69
I/O or Buried - 55 -/- D 2 - - 71
I/O or Buried TDO 56 -/- D 2 32 B7 73
I/O or Buried - 57 3/- D 2 33 A7 75
I/O or Buried - 58 -/- D 2 - - 76
I/O or Buried - 59 -/- D 2 - A6 79
I/O or Buried - 60 -/- D 2 - - 80
I/O or Buried - 61 -/- D 2 - - 81
I/O or Buried - 62 5/6 D 2 34 C5 83
I/O or Buried - 63 -/- D 2 - - 84
I/O or Buried - 64 4/- D 2 35 C4 85
VCCINT - - - - - 17 B3 39
VCCINT - - - - - 41 E4 91
VCCIO - - - - 1 9 E2 3
Function Config. LCell OE MUX LAB IO TQFP UFBGA TQFP
Pin Pin;LCell Bank 44 49 100
Note (10)
VCCIO - - - - 1 - - 18
VCCIO - - - - 1 - - 34
VCCIO - - - - 2 29 C6 51
VCCIO - - - - 2 - - 66
VCCIO - - - - 2 - - 82
GND - - - - - 4 B5 11
GND - - - - - 16 C2 26
GND - - - - - 24 E6 38
GND - - - - - 36 F4 43
GND - - - - - - - 59
GND - - - - - - - 74
GND - - - - - - - 86
GND - - - - - - - 95
No Connect - - - - - - - 1
No Connect - - - - - - - 2
No Connect - - - - - - - 5
No Connect - - - - - - - 7
No Connect - - - - - - - 22
No Connect - - - - - - - 24
No Connect - - - - - - - 27
No Connect - - - - - - - 28
No Connect - - - - - - - 49
No Connect - - - - - - - 50
No Connect - - - - - - - 53
No Connect - - - - - - - 55
Function Config. LCell OE MUX LAB IO TQFP UFBGA TQFP
Pin Pin;LCell Bank 44 49 100
Note (10)
No Connect - - - - - - - 70
No Connect - - - - - - - 72
No Connect - - - - - - - 77
No Connect - - - - - - - 78
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