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The EPM7032B, a member of the MAX® 7000 device family, is based on second-generation MAX architecture and provides 68 registers, and 625 usable gates. The EPM7032AE meets the low power and voltage requirements of 3.3-V applications ranging from notebook computers to battery-operated, hand-held equipment.
EPM7032B devices are available in 44-pin PLCC packages with 32 I/O pins and 44-pin TQFP packages with 32 I/O pins. Each device also contains four dedicated inputs.
The EPM7032B has 32 macrocells divided into 2 LABs. Each macrocell consists of a logic array, a product-term select matrix, and a programmable register. Each macrocell in a LAB can be supplemented with up to 16 shareable expander product terms and 15 high–speed parallel expander product terms to provide up to 32 product terms per macrocell for building complex logic functions. The EPM7032B also supports in-system programmability (ISP) and JTAG BST. The EPM7032B JTAG Instruction Register length is 10 and the JTAG ID code is 270320DD.
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Preliminary support for new device packages may be available for this device. Pin-outs for devices with preliminary support are subject to change. For information on preliminary device support, refer to Quartus® II Software Release Notes, available on the Altera® web site. For complete information on the EPM7032B device, refer to the current MAX 7000B Programmable Logic Device Family Data Sheet, which is available from the Literature section of the Altera web site. |
The following table displays the pin-out information for EPM7032B devices:
Function Config. LCell OE MUX LAB IO PLCC TQFP
Pin Pin;LCell Bank 44 44
Note (10)
Input/GCLK - - -/- - - 43 37
Input/OE1n - - 1/- - - 44 38
Input/GCLRn - - -/- - - 1 39
Input/OE2n/GCLK - - 2/- - - 2 40
I/O or Buried - 1 -/3 A 1 4 42
I/O or Buried - 2 1/- A 1 5 43
I/O or Buried - 3 -/- A 1 6 44
I/O or Buried TDI 4 -/- A 1 7 1
I/O or Buried - 5 -/- A 1 8 2
I/O or Buried - 6 -/4 A 1 9 3
I/O or Buried VREFA 7 6/- A 1 11 5
I/O or Buried - 8 -/5 A 1 12 6
I/O or Buried TMS 9 -/- A 1 13 7
I/O or Buried - 10 -/1 A 1 14 8
I/O or Buried - 11 2/- A 1 16 10
I/O or Buried - 12 3/- A 1 17 11
I/O or Buried - 13 5/- A 1 18 12
I/O or Buried - 14 -/6 A 1 19 13
I/O or Buried - 15 4/- A 1 20 14
I/O or Buried - 16 -/- A 1 21 15
I/O or Buried - 17 -/3 B 2 41 35
I/O or Buried - 18 1/- B 2 40 34
I/O or Buried - 19 -/2 B 2 39 33
I/O or Buried TDO 20 -/- B 2 38 32
I/O or Buried - 21 -/- B 2 37 31
Function Config. LCell OE MUX LAB IO PLCC TQFP
Pin Pin;LCell Bank 44 44
Note (10)
I/O or Buried - 22 -/4 B 2 36 30
I/O or Buried - 23 6/- B 2 34 28
I/O or Buried - 24 -/5 B 2 33 27
I/O or Buried TCK 25 -/- B 2 32 26
I/O or Buried VREFB 26 -/- B 2 31 25
I/O or Buried - 27 2/- B 2 29 23
I/O or Buried - 28 3/- B 2 28 22
I/O or Buried - 29 5/- B 2 27 21
I/O or Buried - 30 -/6 B 2 26 20
I/O or Buried - 31 4/- B 2 25 19
I/O or Buried - 32 -/- B 2 24 18
VCCINT - - - - - 3 17
VCCINT - - - - - 23 41
VCCIO - - - - 1 15 9
VCCIO - - - - 2 35 29
GND - - - - - 10 4
GND - - - - - 22 16
GND - - - - - 30 24
GND - - - - - 42 36
No Connect - - - - - - -
No Connect - - - - - - -
No Connect - - - - - - -
No Connect - - - - - - -
No Connect - - - - - - -
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