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The EM7064AE, a member of the MAX® 7000 device family, is based on second-generation MAX architecture and provides 128 registers, and 1,250 usable gates. The EPM7064AE meets the low power and voltage requirements of 3.3-V applications ranging from notebook computers to battery-operated, hand-held equipment.
EPM7064AE devices are available in 44-pin PLCC packages with 32 I/O pins, 44-pin TQFP packages with 32 I/O pins, 100-pin TQFP packages with 64 I/O pins, and 100-pin FineLine BGA® packages with 64 I/O pins. Each device also contains four dedicated inputs.
The EPM7064AE has 64 macrocells divided into 4 LABs. Each macrocell consists of a logic array, a product-term select matrix, and a programmable register. Each macrocell in a LAB can be supplemented with up to 16 shareable expander product terms and 15 high–speed parallel expander product terms to provide up to 32 product terms per macrocell for building complex logic functions. The EPM7032AE also supports in-system programmability (ISP) and JTAG BST. The EPM7064AE JTAG Instruction Register length is 10 and the JTAG ID code is 170640DD.
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Preliminary support for new device packages may be available for this device. Pin-outs for devices with preliminary support are subject to change. For information on preliminary device support, refer to Quartus® II Software Release Notes, available on the Altera® web site. For complete information on the EPM7064B device, refer to the current MAX 7000A Programmable Logic Device Family Data Sheet, which is available from the Literature section of the Altera web site. |
The following table displays the pin-out information for EPM7064AE devices:
Function Config. LCell OE MUX LAB IO PLCC TQFP TQFP FBGA
Pin Pin;LCell Bank 44 44 100 100
Note (10)
Input/GCLK - - -/- - - 43 37 87 A6
Input/OE1n - - 1/- - - 44 38 88 B6
Input/GCLRn - - -/- - - 1 39 89 B5
Input/OE2n/GCLK - - 3/- - - 2 40 90 A5
I/O or Buried - 1 -/2 A - 12 6 14 F4
I/O or Buried - 2 -/- A - - - 13 E2
I/O or Buried - 3 1/2 A - 11 5 12 E1
I/O or Buried - 4 -/3 A - 9 3 10 D2
I/O or Buried - 5 6/4 A - 8 2 9 D1
I/O or Buried - 6 -/- A - - - 8 D3
I/O or Buried - 7 -/- A - - - 6 C2
I/O or Buried TDI 8 -/- A - 7 1 4 A1
I/O or Buried - 9 -/- A - - - 100 B2
I/O or Buried - 10 -/- A - - - 99 A2
I/O or Buried - 11 3/1 A - 6 44 98 A3
I/O or Buried - 12 -/- A - - - 97 B3
I/O or Buried - 13 -/- A - - - 96 A4
I/O or Buried - 14 5/- A - 5 43 94 B4
I/O or Buried - 15 -/- A - - - 93 C4
I/O or Buried - 16 4/- A - 4 42 92 C5
I/O or Buried - 17 6/5 B - 21 15 37 K5
I/O or Buried - 18 -/- B - - - 36 J5
I/O or Buried - 19 6/4 B - 20 14 35 H5
I/O or Buried - 20 -/5 B - 19 13 33 K4
I/O or Buried - 21 -/2 B - 18 12 32 J4
I/O or Buried - 21 -/- B 2 37 31
Function Config. LCell OE MUX LAB IO PLCC TQFP TQFP FBGA
Pin Pin;LCell Bank 44 44 100 100
Note (10)
I/O or Buried - 22 -/- B - - - 31 H4
I/O or Buried - 23 -/- B - - - 30 J3
I/O or Buried - 24 1/3 B - 17 11 29 K3
I/O or Buried - 25 5/6 B - 16 10 25 K2
I/O or Buried - 26 -/- B - - - 23 H2
I/O or Buried - 27 -/- B - - - 21 G2
I/O or Buried - 28 -/- B - - - 20 G1
I/O or Buried - 29 -/- B - - - 19 G3
I/O or Buried - 30 3/1 B - 14 8 17 F2
I/O or Buried - 31 -/- B - - - 16 F1
I/O or Buried TMS 32 -/- B - 13 7 15 F3
I/O or Buried - 33 -/5 C - 24 18 40 K6
I/O or Buried - 34 -/- C - - - 41 J6
I/O or Buried - 35 6/4 C - 25 19 42 H6
I/O or Buried - 36 -/5 C - 26 20 44 K7
I/O or Buried - 37 -/- C - 27 21 45 J7
I/O or Buried - 38 -/- C - - - 46 H7
I/O or Buried - 39 -/- C - - - 47 J8
I/O or Buried - 40 1/3 C - 28 22 48 K8
I/O or Buried - 41 5/6 C - 29 23 52 K10
I/O or Buried - 42 -/- C - - - 54 J9
I/O or Buried - 43 -/- C - - - 56 G9
I/O or Buried - 44 -/- C - - - 57 G10
I/O or Buried - 45 -/- C - - - 58 G8
I/O or Buried - 46 2/1 C - 31 25 60 F9
Function Config. LCell OE MUX LAB IO PLCC TQFP TQFP FBGA
Pin Pin;LCell Bank 44 44 100 100
Note (10)
I/O or Buried - 47 -/- C - - - 61 F10
I/O or Buried TCK 48 -/- C - 32 26 62 F8
I/O or Buried - 49 -/2 D - 33 27 63 F7
I/O or Buried - 50 -/- D - - - 64 E9
I/O or Buried - 51 1/2 D - 34 28 65 E10
I/O or Buried - 52 -/3 D - 36 30 67 E8
I/O or Buried - 53 6/4 D - 37 31 68 E7
I/O or Buried - 54 -/- D - - - 69 D9
I/O or Buried - 55 -/- D - - - 71 D10
I/O or Buried TDO 56 -/- D - 38 32 73 A10
I/O or Buried - 57 3/- D - 39 33 75 B9
I/O or Buried - 58 -/- D - - - 76 A9
I/O or Buried - 59 -/- D - - - 79 A8
I/O or Buried - 60 -/- D - - - 80 B8
I/O or Buried - 61 -/- D - - - 81 A7
I/O or Buried - 62 5/6 D - 40 34 83 B7
I/O or Buried - 63 -/- D - - - 84 C7
I/O or Buried - 64 4/- D - 41 35 85 C6
VCCINT - - - - - 3 17 39 D5
VCCINT - - - - - 23 41 91 G6
VCCIO - - - - - 15 9 3 C8
VCCIO - - - - - 35 29 18 D4
VCCIO - - - - - - - 34 E6
VCCIO - - - - - - - 51 F5
VCCIO - - - - - - - 66 G7
Function Config. LCell OE MUX LAB IO PLCC TQFP TQFP FBGA
Pin Pin;LCell Bank 44 44 100 100
Note (10)
VCCIO - - - - - - - 82 H3
GND - - - - - 10 4 11 C3
GND - - - - - 22 16 26 D6
GND - - - - - 30 24 38 D7
GND - - - - - 42 36 43 E5
GND - - - - - - - 59 F6
GND - - - - - - - 74 G4
GND - - - - - - - 86 G5
GND - - - - - - - 95 H8
No Connect - - - - - - - 1 B1
No Connect - - - - - - - 2 B10
No Connect - - - - - - - 5 C1
No Connect - - - - - - - 7 C9
No Connect - - - - - - - 22 C10
No Connect - - - - - - - 24 D8
No Connect - - - - - - - 27 E3
No Connect - - - - - - - 28 E4
No Connect - - - - - - - 49 H1
No Connect - - - - - - - 50 H9
No Connect - - - - - - - 53 H10
No Connect - - - - - - - 55 J1
No Connect - - - - - - - 70 J2
No Connect - - - - - - - 72 J10
No Connect - - - - - - - 77 K1
No Connect - - - - - - - 78 K9
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