See Also

You can declare registered outputs of a Text Design File (.tdf) by declaring output ports as flipflops in a Register Declaration in the Variable Section. The reg_out.tdf file shown below has the same functionality as bur_reg.tdf (shown in Declaring Registers), but has registered outputs.

SUBDESIGN reg_out
(
   clk, load, d[7..0] : INPUT;
   q[7..0]            : OUTPUT;
)
VARIABLE
   q[7..0]            : DFFE; % outputs also declared as registers %
BEGIN
   q[].clk = clk;
   q[].ena = load;
   q[] = d[];
END;

When you assign a value to a registered output in the Logic Section, that value drives the d inputs to the registers. The register's output does not change until the rising edge of the clock. In the Logic Section, use <register name>.clk as the clock input to the register. You can implement a global clock in the following ways:

• Use the GLOBAL primitive in a design file.

• Turn on the Global Signal logic option for an individual node. You can assign the Global Signal logic option with the Assignment Organizer command (Assignments menu).

• Turn on the Auto Global Clock logic option to allow the Compiler to choose the signal that feeds the most clock inputs to flipflops as a global clock signal. You can assign the Auto Global Clock logic option with either the Assignment Organizer command or the Default Logic Option Settings page of the Settings dialog box (Assignments menu).

In the example file above, each enable D flipflop (DFFE) declared in the Variable Section feeds an output with the same name, so you can refer to the q outputs of the declared flipflops without using the q port of the flipflops.

In a top-level TDF, output ports are synonymous with output pins. When you declare the same name for an output port and a register, probe and logic option assignments on that name are applied to the pin rather than the register. These identical names prevent you from assigning a probe or a register-specific logic option such as NOT Gate Push-Back. Therefore, if you wish to probe a register or use a register-specific logic option, you must name the registers and ports differently.

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