AHDL

Implementing Bidirectional Pins



The Quartus® II software allows I/O pins in Altera® devices to be configured as bidirectional pins. Bidirectional pins can be specified with a BIDIR port that is connected to the output of a TRI primitive. The signal between the pin and the TRI primitive is a bidirectional signal that can be used to drive other logic in the project.

The bus_reg2.tdf and bus_reg3.tdf files shown below both implement a register that samples the value found on a tri-state bus. It can also drive the stored value back to the bus. One file implements the DFF and TRI primitives with in-line logic function references; the other uses a Register Declaration and Instance Declaration, respectively, in the Variable Section.

SUBDESIGN bus_reg2
(                                        
   clk : INPUT;                             
   oe  : INPUT;                             
   io  : BIDIR;
)                                        
VARIABLE                                 
   dff_out : NODE;                          
                                            
BEGIN                                    
   dff_out = DFF(io, clk, ,);               
   io = TRI(dff_out, oe);                   
END;
SUBDESIGN bus_reg3
(
   clk : INPUT;
   oe  : INPUT;
   io  : BIDIR;
)
VARIABLE
   my_dff  : DFF;
   my_tri  : TRI;
BEGIN
   my_dff.d = io;
   my_dff.clk = clk;

   my_tri.in = my_dff.q;
   my_tri.oe = oe;
   io = my_tri.out;
END;

The bidirectional io signal, driven by TRI, is used as the d input to a D flipflop (DFF).

You can also connect a bidirectional pin from a lower-level Text Design File (.tdf) to a top-level pin. The bidirectional output port of the subdesign should be connected to a bidirectional pin at the top level of the hierarchy. The Function Prototype for the lower-level TDF should include the bidirectional pin in the RETURNS clause. The bidir1.tdf file shown below includes four instances of the bus_reg2 function shown above.

FUNCTION bus_reg2 (clk, oe) RETURNS (io);

SUBDESIGN bidir1
(
   clk, oe  : INPUT;
   io[3..0] : BIDIR;
)
BEGIN
   io0 = bus_reg2(clk, oe);
   io1 = bus_reg2(clk, oe);
   io2 = bus_reg2(clk, oe);
   io3 = bus_reg2(clk, oe);
END;


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