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Consider the following guidelines when working with Text Design Files (.tdf), VHDL Design Files (.vhd), and Verilog Design Files (.v):
(AHDL & VHDL only) All keywords, device names, constants, and primitives should be entered in capital letters; all other text should be lowercase, including file names, megafunctions, and macrofunctions.
| Unformatted: | Formatted: |
case tap is
when test_logic_reset =>
if !tms then
tap = run_test/idle;
end if;
when run_test/idle =>
if tms then
tap = select_dr_scan;
end if;
when select_dr_scan =>
if tms then
tap = select_ir_scan;
else
tap = capture_dr;
end if;
...
end case;
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CASE tap IS
WHEN test_logic_reset =>
IF !tms THEN
tap = run_test/idle;
END IF;
WHEN run_test/idle =>
IF tms THEN
tap = select_dr_scan;
END IF;
WHEN select_dr_scan =>
IF tms THEN
tap = select_ir_scan;
ELSE
tap = capture_dr;
END IF;
...
END CASE;
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(Verilog HDL only) Verilog HDL is case-sensitive; thus, Verilog HDL keywords, built-in gate primitive names, Quartus® II primitive names, Altera-provided megafunctions, and user-defined megafunctions and macrofunctions must be in lowercase. All constants should be entered in capital letters. Identifiers can be a mixture of lowercase and capital letters.
| Unformatted: | Formatted: |
MODULE example (A, b, c);
INPUT A, b;
output c;
reg c;
PARAMETER example1 = 0,
example2 = 1;
always @ (A) begin
IF (b)
c = example1;
ELSE
c = example2;
end
endmodule
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module example (a, b, c);
input a, b;
output c;
reg c;
parameter EXAMPLE1 = 0,
EXAMPLE2 = 1;
always @ (a) begin
if (b)
c = EXAMPLE1;
else
c = EXAMPLE2;
end
endmodule
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(AHDL & VHDL only) Either list all input and output ports on the same line, or type :INPUT; (AHDL) or :IN (VHDL) after each line of inputs and :OUTPUT; (AHDL) or :OUT (VHDL) after each line of outputs. With this formatting style, all ports are clearly labeled.
(Verilog HDL only) Either list all input and output ports on the same line, or type input before each line of inputs and output before each line of outputs. With this formatting style, all ports are clearly labeled.
Lines should not be longer than the width of the screen. If necessary, move part of a line to the next line and indent it. The Text Editor provides an auto-indent feature and the Increase Indent and Decrease Indent commands (Edit menu) to help you indent text.
(AHDL only) Place opening and closing parentheses (()) of the Subdesign Section and of Parameters Statements on a separate line to easily distinguish inputs and outputs. This formatting style also allows you to add and edit signal and parameter names easily.
| Unformatted: | Formatted: |
SUBDESIGN s (i1, i2, i3: INPUT;
o1, o2, o3: OUTPUT;)
BEGIN
...
END;
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SUBDESIGN s
(
i1, i2, i3 : INPUT;
o1, o2, o3 : OUTPUT;
)
BEGIN
...
END;
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(AHDL only) Do not use quoted symbolic names if you can use unquoted names.
| Unformatted: | Formatted: |
VARIABLE
tap: MACHINE WITH STATES (
'Test-Logic-Reset',
'Run-Test/Idle',
'Select-DR-Scan',
'Capture-DR',
'Shift-DR',
'Exit1-DR',
'Pause-DR',
'Exit2-DR',
'Update-DR',
'Select-IR-Scan',
'Capture-IR',
'Shift-IR',
'Exit1-IR',
'Pause-IR',
'Exit2-IR',
'Update-IR');
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VARIABLE
tap: MACHINE WITH STATES (
test_logic_reset,
run_test_idle,
select_dr_scan,
capture_dr,
shift_dr,
exit1_dr,
pause_dr,
exit2_dr,
update_dr,
select_ir_scan,
capture_ir,
shift_ir,
exit1_ir,
pause_ir,
exit2_ir,
update_ir);
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- PLDWorld - |
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