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Consider the following guidelines when working with Text Design Files (.tdf), VHDL Design Files (.vhd), and Verilog Design Files (.v):

• Describe the design at the beginning of the Text Design File, VHDL Design File, or Verilog Design File with a substantial comment in plain language. Specifically, describe the ports and function of the design.

• Use comments where appropriate to document the file. These comments should provide relevant information about the corresponding statement, and should be updated along with the file.

• Do not duplicate a statement as a comment.

  With Duplication:	Without Duplication:
  IF clear THEN % load q[] with 0 % q[] = 0; END IF;	IF clear THEN q[] = 0; END IF;

  
  

• Place a comment either directly above the section it describes at the same indentation level, or aligned with other comments to the right of the lines of code.

• Leave one blank space between documentation text and the comment delimiter: (a percent symbol (%) for AHDL comments; two dashes (--) for VHDL comments; or /*, */, and // for Verilog HDL comments). Align the opening and closing symbols for easy readability.

  Unformatted:	Formatted:
  %Leave one blank space between% %the percent symbol and the% %documenting text. Line up% %opening and closing percent% %symbols for easy readability.%	% Leave one blank space between % % the percent symbol and the % % documenting text. Line up % % opening and closing percent % % symbols for easy readability. %

  
  

• (AHDL only) You can nest VHDL-style (--) comments within %-style comments in AHDL files. If you use VHDL-style comments for documentation comments, you can then use the %-style comments to exclude (as in, comment out) sections of code from compilation.

• (Verilog HDL only) You can nest one-line comments within block comments. If you use one-line comments (//) for documentation comments, you can then use the /*-style comments to exclude (as in, comment out) sections of code from compilation.

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