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Consider the following guidelines when working with Text Design Files (.tdf), VHDL Design Files (.vhd), and Verilog Design Files (.v):

• Names must use only legal name characters. Also, you cannot use keywords as names in VHDL or Verilog HDL, and you cannot use them in AHDL unless they are "escaped." Go to Reserved Keywords and Reserved Identifiers for more details on using AHDL keywords as names.

• All symbolic names and identifiers should be meaningful and completely understandable, and should reflect the purpose or action of the function.

  Ambiguous Name:	Unambiguous Name:
  direction access_mode	up access_memory

  
  

• Active-low signals should be specified with a clear and consistent notation. The notations shown below are supported in Quartus^® II design files. You should choose one notation and use it throughout a project.

  /write (not available in VHDL or Verilog HDL)
  nchip_enable
resetn

• Use underscores (_) to separate "words" in symbolic and simple names.

  Unformatted:	Formatted:
  regload idleio goidle CSYNCPREEQJ	reg_load idle_io go_idle CSYNC_PRE_EQ_J

  
  

• Do not use abbreviations unless they are obvious.

  Ambiguous Name:	Unambiguous Name:
  c clrg sb sm rdrm f r	clk clear_reg sync_bit select_mem refresh_dram forward reverse

  
  

• (AHDL only) The Title Statement should include a short, descriptive name for the design.

  TITLE "NTSC Waveform Generator";

• Replace numbers with constants (or, in Verilog HDL, parameters) to provide meaningful names and a visual reference for all numbers. Only use 0 and 1 (AHDL & Verilog HDL) or '0' and '1' (VHDL) in the code.

  CONSTANT TERMINAL_COUNT = 103;

  parameter TERMINAL_COUNT = 103;

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