Closed-Loop Power Supply Margining

Dynamically alter the precise value of power supply voltage.

Closed-loop power supply margining is a technique whereby a power rail is continuously monitored and the system can force the rail to go up or down in very small increments.

Some of the benefits of doing this are as follows:

• Better margin for the power supply rail. Dynamically adjusting the rail to maintain the ideal nominal value negates aging, tolerance, and temperature effects to the resistors that set the voltage value.
• Ability to reduce the power supply's voltage in order to reduce overall power consumption. Since the closed-loop controller can make very small adjustments to the power supply's output value, the power supply can be kept at a lower than nominal value but still within the tolerance of all devices on that rail.
• Ability to increase the power supply's voltage above nominal value. In this case, the devices on a given supply rail can benefit from a slight performance increase, and all devices are still guaranteed to operate within their maximum limits.
• Manufacturer's power supply margin verification. Closed-loop margining allows manufacturers to track the point at which failures occur, providing the manufacturer with records of the actual margin for each board that goes through production. These records provide valuable reliability data to manufacturers.

The challenge in implementing closed-loop margining in an FPGA is the need for an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). Fusion addresses this problem by providing a built-in ADC and design files for a specialized block that creates a DAC using an external RC low-pass filter. For

instance, in Actel's Fusion mixed-signal FPGA, a 12-bit low-ripple DAC design using a single-pole RC filter, utilizes 51 logic tiles and can easily achieve μV ripple with update rates in excess of 1 kHz. This newer type of DAC is referred to as "Low Ripple DAC". The Low Ripple DAC was specifically designed for Fusion because of its inherent ability to act as a power supervisor, sequencer, and marginer, but could easily be used in a variety of other applications where low output impedance, low ripple, high bandwidth, and small size are important.

Evaluation of Low Ripple DAC against pulse width modulation (PWM) DAC can be done using the Low Ripple Calculator available for download from Actel's website.

By using the Low Ripple DAC block and an RC filter to create a DAC, it is now possible to margin power supplies from the digital output of Actel's Fusion mixed-signal FPGAs at almost no extra cost or board space. The output impedance, bandwidth, and ripple more than satisfy the requirements for power supply margining. In addition, it is now possible to create several trim DACs because of the high number of outputs typically available on Fusion. Finally, with Fusion's 30 channels of ADC inputs, it is possible to supervise, sequence, and perform closed- or open-loop margining on several power supplies from a single chip.

No other solution in the industry provides the user with more flexibility: choice of algorithm, implementation style, and DAC precision. This added flexibility also significantly reduces risk in the event that the design requires unforeseen changes.

To begin designing with Fusion today, you can download and license the FREE Libero IDE software and Low Ripple DAC design example. In order to try out the design onboard and for more information, refer to the closed-loop margining application note for details on the Fusion System Development Kit and Linear Technology Daughter Card.