Flash*Freeze Static Power < 5 µW

Enter and Exit Flash*Freeze Mode within 1 µs.

Actel IGLOO, IGLOO PLUS, and ProASIC3L FPGAs include Flash*Freeze technology and are designed to meet the most demanding power and area challenges of today's portable electronics products with reprogrammable, small-footprint, full-featured flash FPGAs.

Flash*Freeze technology provides an ultra-low-power static mode (Flash*Freeze mode) that retains all SRAM and register information with rapid recovery to active (operating) mode. IGLOO PLUS has an additional feature when operating in Flash*Freeze mode, allowing it to retain I/O states as well as SRAM and register states. This mechanism enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the Flash*Freeze (FF) pin while all power supplies are kept in their original states. In addition, I/Os and clocks connected to the FPGA can still be driven or toggling without impact on device power consumption. Flash*Freeze mode can be configured so that no power is consumed by the I/O banks, clocks, JTAG pins, or PLLs, and the IGLOO and IGLOO PLUS devices consume as little as 5 µW. Actel offers a state management IP core to aid users in gating clocks and managing data before entering Flash*Freeze mode.

Flash*Freeze technology enables the user to switch to Flash*Freeze mode within 1 µs, thus simplifying low-power design implementation. The Flash*Freeze (FF) pin (active low) is a dedicated pin used to enter or exit Flash*Freeze mode directly, or the pin can be routed internally to the FPGA core to allow the user's logic to decide if and when it is safe to transition to this mode. If the FF pin is not used, it can be used as a regular I/O. The FF pin has a built-in glitch filter to prevent entering or exiting Flash*Freeze mode accidentally. There are two ways to use Flash*Freeze mode:

• In Flash*Freeze mode type 1, entering and exiting the mode is exclusively controlled by the assertion and deassertion of the FF pin.
• In Flash*Freeze mode type 2, entering the mode is controlled by both the FF pin AND the user-defined LSICC signal available in the ULSICC macro. Exiting the mode is controlled by either the FF pin OR the user-defined LSICC signal.

If a system requires the device to be instantly on at power-up, it makes sense to do any housekeeping tasks before switching the device into Flash*Freeze mode. On the other hand, if the important thing is to get the device off as quickly as possible, then there may be an initialization routine that is followed when the device comes out of Flash*Freeze mode. These options will be specific to each design application, so the Flash*Freeze IP and handbook section helps designers through these steps. To begin designing with any of the families that support Flash*Freeze mode, you can download and license the FREE Libero IDE software. Or to measure power and view results of Flash*Freeze mode, you can purchase the low-cost IGLOO Icicle Demonstration Kit.