Using DDR Interface with Actel's Flash FPGAs
Double-data-rate (DDR) interface in Actel devices provides a migration path from single-data-rate (SDR) memory interface to a faster interface for enhanced applications.
DDR memory interface doubles the bandwidth of the device without increasing the clock speed or bus width. DDR SDRAM provides a source-synchronous data capture at a rate of twice the clock frequency. These devices utilize 2n-prefetch architecture where the internal data bus is twice the size of the external data bus. The core of a DDR interface is similar to an SDR interface with identical address and control, bank structures, and refresh requirements. The main difference between DDR and SDR interfaces is in the actual data interface. SDR is fully synchronous using the positive edge of the clock. DDR is true source-synchronous and captures data twice per clock cycle.
Summary of enhancements for DDR:
- DDR utilizes a differential pair for the system clock
- Data is transmitted on both positive and negative edges of the clock
- SSTL-2 signaling is used
A good example of using DDR I/Os is in an application where the FPGA is reading data from an external memory, an FPGA, or another external device.
The data enters the FPGA through a pad and is captured into a DDR register, which splits the data into two outputs: QR and QF. QR is the output at the rising edge of the clock, and QF is at the falling edge of the clock. The data is registered into a dual-port SRAM in Actel's ProASIC®3 FPGA. Control logic circuitry is used to control the address space to write data coming from DDR I/O registers to SRAM blocks inside the FPGA for internal processing.
Simultaneously, the data can be sent from an SRAM block through an output DDR register to an external device in the same clock cycle. This doubles the speed of the data throughput into the FPGA, as compared to SDR, where each bit is captured and registered at every clock edge. With this technique, multiple bits of data can fill several addresses of RAM in fewer cycles. Similarly, the data can be sent to an upstream device via an output register and reduce the total number of pins used.
Actel provides reference designs and a development board that is used to demonstrate the communication path from a PCI bus to external DDR memory. To learn more about the DDR memory interface in Actel's flash-based FPGA, read Using DDR for ProASIC3/E App Note.
