Actel

Summer 2007

innovative power smart solutions

IGLOOIGLOO 5 μW FPGAs

— the Smart Choice for Low Power

Compared with industry-leading low power CPLDs, IGLOO FPGAs, with static power as low as 5 µW, deliver more complexity and features than CPLDs, with four times lower static power and as much as five times longer battery life in portable applications.

IGLOO vs CPLDs Static Power

Then compare with today's "low power" best-of-breed SRAM-based FPGAs, Actel's flash-based IGLOO FPGAs deliver between one hundred and one thousand times improvement in power reduction. This two to three orders of magnitude lower static power consumption can translate into weeks and months of standby battery life. Use the Power Calculator or SmartPower to see how IGLOO will perform in your design.

 
Flash*Freeze

The IGLOO device has an ultra low-power static mode, called Flash*Freeze mode, which retains all SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology enables the user to quickly enter and exit Flash*Freeze mode, within
1 µs, by activating the Flash*Freeze pin while all power supplies are kept at their original values.

  • I/Os and global I/Os can still be driven and can be toggling without impact on power consumption
  • Clocks can still be driven or can be toggling without impact on power consumption
  • Internal clocks from PLLs are automatically disabled
  • Device retains all core register, SRAM information, and states
  • I/O states are tristate during Flash*Freeze mode or can be set using weak pull-up or pull-down attribute
  • No power is consumed by the I/O banks, clocks, JTAG pins, or PLL
  • IGLOO devices consume as little as 5 µW in this mode.

Flash*Freeze Usage type 1

In Flash*Freeze mode type 1, entering and exiting the mode is exclusively controlled by the assertion and de-assertion of the FF pin.

IGLOO Flash FPGAsThe device will enter Flash*Freeze mode 1 µs after the dedicated FF pin is asserted and returns to normal operation when the FF pin is deasserted. This mode is implemented by enabling Flash*Freeze mode (default setting) in the Actel Designer software. The FF pin threshold voltages are defined by VCCI and the supported single-ended I/O standard in the corresponding I/O bank. The FF pin has a built-in glitch filter that ensures spurious glitches are filtered out to prevent entering or exiting Flash*Freeze mode accidentally.

Flash*Freeze Usage type 2

In Flash*Freeze mode type 2, entering and exiting the mode is controlled by both the FF pin AND the user-controlled logic.

Flash*Freeze TechnologyThe device can enter Flash*Freeze mode by activating the FF pin together with other user-defined control logic or delay circuitry within the FPGA core. This method enables the design to perform important activities before allowing the device to enter Flash*Freeze mode, such as transitioning into a safe state or completing the processing of a critical event. The device will only enter Flash*Freeze mode when the Flash*Freeze pin is asserted and the ULSICC macro input signal, called the LSICC signal, is asserted.

 

For IGLOO information, visit: actel.com/products/IGLOO