Actel

Summer 2007

innovative power smart solutions

Accelerating Design Entry with Libero IDE v8.0

In the FPGA space, time-to-market is always a key factor. It is one of the reasons to use an FPGA instead of an ASIC.

It has become the standard for FPGA vendors or third parties to create IP, solutions, and reference designs to get you through your design process as quickly as possible. Building your design often becomes a jigsaw of different formats, tools, blocks, and styles working together.

Within the Actel portfolio alone, there are multiple options:
  • SmartGen cores are configurable standard blocks, as well as Fusion design elements.
  • IP Catalog gives access to over 100 industry-standard functions, either from Actel or third-party suppliers.
  • CoreConsole can create a processor IP with subsystem to drop into your FPGA fabric.

Download Libero IDE v8.0 »

SmartDesignSmartDesign

SmartDesign Canvas

SmartDesign allows you take design elements from the options mentioned above and drop them onto one Canvas, bringing them all into the same playing field. Instead of trying to create and navigate through all the VHDL port maps and connections, you can drop the blocks in and then use the Connectivity Grid to create all your connections. Best of all, you can automatically export a completed VHDL or Verilog file to use at the top level of your design. Fusion analog system and bus interface connections can be made by SmartDesign automatically.

It is presumptuous to assume that your entire design is done for you as a simple jigsaw, so SmartDesigntake your own HDL blocks, add them to the Hierarchy, and drop them onto the Canvas to interface with the standard blocks.

Connectivity Grid

For other device connections, a connections grid displays the blocks in a matrix layout, where intersecting cells become "connection opportunity" points. Pull-down menus display available ports where selections can be easily made and then visually verified.

Schematic View

Connections on the Canvas are simplified to keep the view clean, but the Schematic view allows you to see all the connections, providing a good sanity check of what you have been working on.

Design Checking and Fusion Design Assistance

Illegal connections are not possible from the grid intersections, preventing possible typos and misconnects of manual entry. SmartDesign creates "correct by construction" HDL source code. SmartDesign understands core dependencies to other cores and busses in Fusion designs, and provides menus and descriptions that allow you to quickly and easily determine the correct solution. SmartDesign then automatically connects the blocks. With SmartDesign's understanding of Fusion Analog and Memory System Builders and autoconnections, plus visual presentations, connections, and verifications performed using the Connectivity Grid, Canvas, and Schematic views, using SmartDesign greatly reduces your design time and eliminates errors.

For SmartDesign visit: actel.com/ezone/smartdesign