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The ATL RASSP team developed the model-year architecture to promote design upgrades and reuse via standardized, open interfaces while leveraging state-of-the-art commercial technology developments. What drives the RASSP signal processor architecture are the requirements imposed on signal processors to meet changing mission-critical processing needs, and the military's requirements for long-term life cycle support. RASSP must also address the full spectrum of signal processing applications, both commercial and military: This range of requirements imposes a formidable challenge: defining an architectural approach that addresses low-cost technology insertion, upgradability, and extensibility.
Model-year architectures must support scalability, heterogeneity, open interfaces, modular software, life cycle support, testability, and system retrofit. The notion of model-year upgrades is embodied in reuse libraries and the methodology for their use. The hardware and software elements within the libraries are "encapsulated" by functional wrappers. Adding this level of abstraction hides implementation details. It also makes practical technology insertion, reuse, trade-offs, and optimizations for specific applications.
Recently, the applicability of this technology was extended into the System-on-a-Chip arena. This technology is the basis for the Virtual Socket Interface Alliance [VSIA] bus wrapper technology, enabling system designers to quickly interconnect Intellectual Property (IP cores) from different vendors on a single chip. 1.0 Executive Summary
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