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mti_GetSignalNameIndirect()
Gets the full simple name of a VHDL signal including array indices and record subelement names.
Syntax
signal_name = mti_GetSignalNameIndirect( signal_id, buffer, length )Returns
Name Type Description signal_name char * The full simple name of the specified signalArguments
Description
mti_GetSignalNameIndirect() returns the full simple name of the specified VHDL signal including array indices and record fields. If the buffer parameter is NULL, then mti_GetSignalNameIndirect() allocates memory for the name and returns a pointer to it. The caller is responsible for freeing this memory with mti_VsimFree(). If the buffer parameter is not NULL, then mti_GetSignalNameIndirect() copies the name into the buffer parameter up to the length specified by the length parameter and also returns a pointer to the buffer parameter.
Related functions
Example
FLI code
#include <mti.h> static void printSignalInfo( mtiSignalIdT sigid, int indent ) { char * signame; int i; mtiSignalIdT * elem_list; mtiTypeIdT sigtype; sigtype = mti_GetSignalType( sigid ); signame = mti_GetSignalNameIndirect( sigid, 0, 0 ); mti_PrintFormatted( "%*c%s\n", indent, ' ', signame ); mti_VsimFree( signame ); switch ( mti_GetTypeKind( sigtype ) ) { case MTI_TYPE_ARRAY: elem_list = mti_GetSignalSubelements( sigid, 0 ); switch ( mti_GetTypeKind( mti_GetArrayElementType( sigtype )) ) { case MTI_TYPE_ARRAY: case MTI_TYPE_RECORD: for ( i = 0; i < mti_TickLength( sigtype ); i++ ) { printSignalInfo( elem_list[i], indent+2 ); } break; default: for ( i = 0; i < mti_TickLength( sigtype ); i++ ) { signame = mti_GetSignalNameIndirect( elem_list[i], 0, 0 ); mti_PrintFormatted( "%*c %s\n", indent, ' ', signame ); mti_VsimFree( signame ); } break; } mti_VsimFree( elem_list ); break; case MTI_TYPE_RECORD: elem_list = mti_GetSignalSubelements( sigid, 0 ); for ( i = 0; i < mti_GetNumRecordElements( sigtype ); i++ ) { switch ( mti_GetTypeKind( mti_GetSignalType( elem_list[i] )) ) { case MTI_TYPE_ARRAY: case MTI_TYPE_RECORD: printSignalInfo( elem_list[i], indent+2 ); break; default: signame = mti_GetSignalNameIndirect( elem_list[i], 0, 0 ); mti_PrintFormatted( "%*c %s\n", indent, ' ', signame ); mti_VsimFree( signame ); break; } } mti_VsimFree( elem_list ); break; default: break; } } void loadDoneCB( void * param ) { mti_PrintMessage( "\nComposite Signals:\n" ); mti_PrintMessage( " Signal /top/s1:" ); printSignalInfo( mti_FindSignal( "/top/s1" ), 4 ); mti_PrintMessage( " Signal /top/s2:" ); printSignalInfo( mti_FindSignal( "/top/s2" ), 4 ); mti_PrintMessage( " Signal /top/s3:" ); printSignalInfo( mti_FindSignal( "/top/s3" ), 4 ); mti_PrintMessage( " Signal /top/s4:" ); printSignalInfo( mti_FindSignal( "/top/s4" ), 4 ); mti_PrintMessage( " Signal /top/s5:" ); printSignalInfo( mti_FindSignal( "/top/s5" ), 4 ); mti_PrintMessage( " Signal /top/s6:" ); printSignalInfo( mti_FindSignal( "/top/s6" ), 4 ); } void initForeign( mtiRegionIdT region, /* The ID of the region in which this */ /* foreign architecture is instantiated. */ char *param, /* The last part of the string in the */ /* foreign attribute. */ mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/ mtiInterfaceListT *ports /* A list of ports for the foreign model. */ ) { mti_AddLoadDoneCB( loadDoneCB, 0 ); }HDL code
entity for_model is end for_model; architecture a of for_model is attribute foreign of a : architecture is "initForeign for_model.sl"; begin end a; entity top is type rectype is record a : integer; b : bit; c : bit_vector( 3 downto 0 ); end record; type rectype2 is record f1 : bit; f2 : rectype; end record; type a1 is array ( 2 downto 0 ) of bit; type a2 is array ( 3 downto 2 ) of a1; type a3 is array ( 1 to 2, 0 to 4 ) of character; end top; architecture a of top is signal s1 : bit := '0'; signal s2 : rectype := ( 42, '1', "1100" ); signal s3 : bit_vector( 7 downto 0 ) := "10001111"; signal s4 : rectype2 := ( '1', ( 16, '0', "1111" ) ); signal s5 : a2 := ( "101", "011" ); signal s6 : a3 := ( "Hello", "there" ); component for_model is end component; for all : for_model use entity work.for_model(a); begin i1 : for_model; s1 <= not s1 after 5 ns; end a;Simulation output
% vsim -c top Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl # 5.4b # vsim -c top # Loading .../modeltech/sunos5/../std.standard # Loading work.top(a) # Loading work.for_model(a) # Loading ./for_model.sl # # Composite Signals: # Signal /top/s1: # s1 # Signal /top/s2: # s2 # s2.a # s2.b # s2.c # s2.c(3) # s2.c(2) # s2.c(1) # s2.c(0) # Signal /top/s3: # s3 # s3(7) # s3(6) # s3(5) # s3(4) # s3(3) # s3(2) # s3(1) # s3(0) # Signal /top/s4: # s4 # s4.f1 # s4.f2 # s4.f2.a # s4.f2.b # s4.f2.c # s4.f2.c(3) # s4.f2.c(2) # s4.f2.c(1) # s4.f2.c(0) # Signal /top/s5: # s5 # s5(3) # s5(3)(2) # s5(3)(1) # s5(3)(0) # s5(2) # s5(2)(2) # s5(2)(1) # s5(2)(0) # Signal /top/s6: # s6 # s6(1) # s6(1)(0) # s6(1)(1) # s6(1)(2) # s6(1)(3) # s6(1)(4) # s6(2) # s6(2)(0) # s6(2)(1) # s6(2)(2) # s6(2)(3) # s6(2)(4) VSIM 1> quit
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