mti_GetSignalName()

Gets the simple name of a scalar or top-level composite VHDL signal.

Syntax

signal_name = mti_GetSignalName( signal_id ) 

Returns

Name	Type	Description
signal_name	char *	The simple name of the signal

Arguments

Name	Type	Description
signal_id	mtiSignalIdT	A handle to a VHDL signal

Description

mti_GetSignalName() returns the simple name of the specified VHDL signal. If the signal is a composite subelement, then the name returned is the name of the top-level composite. The returned pointer must not be freed.

To get the name of a composite subelement signal, use mti_GetSignalNameIndirect().

Related functions

mti_GetSignalNameIndirect()

Example

FLI code

#include <mti.h>

void printSignals( mtiRegionIdT region, int indent )
{
  mtiSignalIdT sigid;

  for ( sigid = mti_FirstSignal( region ); sigid;
        sigid = mti_NextSignal() ) {
    if ( sigid ) {
      mti_PrintFormatted( "%*cSignal %s\n",
                         indent, ' ', mti_GetSignalName( sigid ) );
    }
  }
}

void printHierarchy( mtiRegionIdT region, int indent )
{
  char *       region_name;
  mtiRegionIdT regid;

  region_name = mti_GetRegionFullName( region );
  mti_PrintFormatted( "%*cRegion %s\n", indent, ' ', region_name );
  indent += 2;
  printSignals( region, indent );
  for ( regid = mti_FirstLowerRegion( region );
        regid; regid = mti_NextRegion( regid ) ) {
    printHierarchy( regid, indent );
  }
  mti_VsimFree( region_name );
}

void loadDoneCB( void * param )
{
  mtiSignalIdT * elem_list;
  mtiSignalIdT   sigid;

  mti_PrintMessage( "\nLoad Done phase:\n" );
  printHierarchy( mti_GetTopRegion(), 1 );

  mti_PrintMessage( "\nTesting names of composite subelements:\n" );
  sigid = mti_FindSignal( "/top/inst1/s3" );
  elem_list = mti_GetSignalSubelements( sigid, 0 );
  mti_PrintFormatted( "  Signal %s\n", mti_GetSignalName( elem_list[1] ) );
  mti_VsimFree( elem_list );
  sigid = mti_FindSignal( "/top/inst1/s4" );
  elem_list = mti_GetSignalSubelements( sigid, 0 );
  mti_PrintFormatted( "  Signal %s\n", mti_GetSignalName( elem_list[0] ) );
  mti_VsimFree( elem_list );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( loadDoneCB, 0 );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl";
begin
end a;

entity inv is
  generic ( delay : time := 5 ns );
  port ( a : in bit;
         b : out bit
       );
end inv;

architecture b of inv is
  signal count : integer := 0;
begin
  b <= a after delay;

  p1 : process( a )
  begin
    count <= count + 1 after 0 ns;
  end process;
end b;

entity mid is

  type rectype is record
    a : integer;
    b : bit;
    c : bit_vector( 3 downto 0 );
  end record;

end mid;

architecture a of mid is

  signal s1 : bit := '0';
  signal s2 : bit := '0';
  signal s3 : rectype := ( 42, '1', "1100" );
  signal s4 : bit_vector( 7 downto 0 ) := "10001111";

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

  component inv is
    generic ( delay : time := 5 ns );
    port ( a : in bit;
           b : out bit
         );
  end component;

begin

  i1 : for_model;

  s1 <= not s1 after 5 ns;

  toggle : inv port map ( s1, s2 );

end a;

entity top is
end top;

architecture a of top is
  component mid is
  end component;
begin
  inst1 : mid;
end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading work.mid(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
# Loading work.inv(b)
# 
# Load Done phase:
#  Region /top
#    Region /top/inst1
#      Signal s1
#      Signal s2
#      Signal s3
#      Signal s4
#      Region /top/inst1/i1
#      Region /top/inst1/toggle
#        Signal a
#        Signal b
#        Signal count
# 
# Testing names of composite subelements:
#   Signal s3
#   Signal s4
VSIM 1> quit 

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