mti_GetSignalMode()

Gets the mode (direction) of a VHDL signal.

Syntax

direction = mti_GetSignalMode( signal_id ) 

Returns

Name	Type	Description
direction	mtiDirectionT	The port mode of the specified signal

Arguments

Name	Type	Description
signal_id	mtiSignalIdT	A handle to a VHDL signal

Description

mti_GetSignalMode() returns the direction (or port mode) of the specified VHDL signal. The direction is one of the following: MTI_INTERNAL, MTI_DIR_IN, MTI_DIR_OUT, or MTI_DIR_INOUT. MTI_INTERNAL indicates that the signal is not a port.

Related functions

None

Example

FLI code

#include <mti.h>

static char * convertDirection( mtiDirectionT direction )
{
  switch ( direction ) {
    case MTI_INTERNAL:  return "INTERNAL";
    case MTI_DIR_IN:    return "IN";
    case MTI_DIR_OUT:   return "OUT";
    case MTI_DIR_INOUT: return "INOUT";
    default:            return "UNKNOWN";
  }
}

void printSignals( mtiRegionIdT region, int indent )
{
  mtiSignalIdT sigid;

  for ( sigid = mti_FirstSignal( region ); sigid;
        sigid = mti_NextSignal() ) {
    if ( sigid ) {
      mti_PrintFormatted( "%*cSignal %s: Direction is %s\n",
                         indent, ' ', mti_GetSignalName( sigid ),
                         convertDirection( mti_GetSignalMode( sigid )));
    }
  }
}

void printHierarchy( mtiRegionIdT region, int indent )
{
  char *       region_name;
  mtiRegionIdT regid;

  region_name = mti_GetRegionFullName( region );
  mti_PrintFormatted( "%*cRegion %s\n", indent, ' ', region_name );
  indent += 2;
  printSignals( region, indent );
  for ( regid = mti_FirstLowerRegion( region );
        regid; regid = mti_NextRegion( regid ) ) {
    printHierarchy( regid, indent );
  }
  mti_VsimFree( region_name );
}

void loadDoneCB( void * param )
{
  mti_PrintMessage( "\nLoad Done phase:\n" );
  printHierarchy( mti_GetTopRegion(), 1 );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( loadDoneCB, 0 );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl";
begin
end a;

entity inv is
  generic ( delay : time := 5 ns );
  port ( a : in bit;
         b : out bit
       );
end inv;

architecture b of inv is
  signal count : integer := 0;
begin
  b <= a after delay;

  p1 : process( a )
  begin
    count <= count + 1 after 0 ns;
  end process;
end b;

library ieee;
use ieee.std_logic_1164.all;

entity mid is
  port ( ptio : inout std_logic );
end mid;

architecture a of mid is

  signal s1 : bit := '0';
  signal s2 : bit := '0';
  signal s3 : bit := '0';
  signal s4 : bit := '0';

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

  component inv is
    generic ( delay : time := 5 ns );
    port ( a : in bit;
           b : out bit
         );
  end component;

begin

  flip : inv port map ( s3, s4 );

  i1 : for_model;

  s1 <= not s1 after 5 ns;
  s3 <= not s3 after 5 ns;

  toggle : inv port map ( s1, s2 );

  p1 : process
    begin
      ptio <= 'U';
      wait for 1 ns;
      ptio <= 'Z';
      wait for 30 ns;
    end process;

end a;

library ieee;
use ieee.std_logic_1164.all;

entity top is
end top;

architecture a of top is
  component mid is
    port ( ptio : inout std_logic );
  end component;

  signal sls : std_logic := '0';
begin
  inst1 : mid port map ( sls );
  sls <= std_logic'val( std_logic'pos(sls) + 1 ) after 5 ns;
end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.top(a)
# Loading work.mid(a)
# Loading work.inv(b)
# Loading work.for_model(a)
# Loading ./for_model.sl
# 
# Load Done phase:
#  Region /top
#    Signal sls: Direction is INTERNAL
#    Region /top/inst1
#      Signal ptio: Direction is INOUT
#      Signal s1: Direction is INTERNAL
#      Signal s2: Direction is INTERNAL
#      Signal s3: Direction is INTERNAL
#      Signal s4: Direction is INTERNAL
#      Region /top/inst1/flip
#        Signal a: Direction is IN
#        Signal b: Direction is OUT
#        Signal count: Direction is INTERNAL
#      Region /top/inst1/i1
#      Region /top/inst1/toggle
#        Signal a: Direction is IN
#        Signal b: Direction is OUT
#        Signal count: Direction is INTERNAL
VSIM 1> quit 

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