mti_SignalImage()

Gets the string image of a VHDL signal's value.

Syntax

value = mti_SignalImage( signal_id ) 

Returns

Name	Type	Description
value	char *	A string image of the specified signal's value

Arguments

Name	Type	Description
signal_id	mtiSignalIdT	A handle to a VHDL signal

Description

mti_SignalImage() returns a pointer to a static buffer containing the string image of the value of the specified signal. The image is the same as would be returned by the VHDL 1076-1993 attribute 'IMAGE. The returned string is valid only until the next call to any FLI function. This pointer must not be freed.

Related functions

mti_GetArraySignalValue()

mti_GetSignalValue()

mti_GetSignalValueIndirect()

Example

FLI code

#include <mti.h>

typedef struct signalInfoT_tag {
  struct signalInfoT_tag * next;
  char                   * name;
  mtiSignalIdT             sigid;
  mtiTypeIdT               typeid;
} signalInfoT;

typedef struct {
  signalInfoT   * sig_info;     /* List of signals. */
  mtiProcessIdT   proc;         /* Test process id. */
} instanceInfoT;

static void checkValues( void *inst_info )
{
  instanceInfoT *inst_data = (instanceInfoT *)inst_info;
  signalInfoT   *siginfo;

  mti_PrintFormatted( "Time [%d,%d]:\n", mti_NowUpper(), mti_Now() );

  for ( siginfo = inst_data->sig_info; siginfo; siginfo = siginfo->next ) {
    mti_PrintFormatted( "  Signal %s = %s\n", siginfo->name,
                       mti_SignalImage( siginfo->sigid ) );
  }

  mti_ScheduleWakeup( inst_data->proc, 5 );
}

static signalInfoT * setupSignal( mtiSignalIdT sigid )
{
  signalInfoT * siginfo;

  siginfo          = (signalInfoT *) mti_Malloc( sizeof(signalInfoT) );
  siginfo->sigid   = sigid;
  siginfo->name    = mti_GetSignalNameIndirect( sigid, 0, 0 );
  siginfo->typeid  = mti_GetSignalType( sigid );
  siginfo->next    = 0;

  return( siginfo );
}

static void initInstance( void )
{
  instanceInfoT * inst_data;
  mtiSignalIdT    sigid;
  signalInfoT   * curr_info;
  signalInfoT   * siginfo;

  inst_data           = mti_Malloc( sizeof(instanceInfoT) );
  inst_data->sig_info = 0;

  for ( sigid = mti_FirstSignal( mti_GetTopRegion() );
        sigid; sigid = mti_NextSignal() ) {
    siginfo = setupSignal( sigid );
    if ( inst_data->sig_info == 0 ) {
      inst_data->sig_info = siginfo;
    }
    else {
      curr_info->next = siginfo;
    }
    curr_info = siginfo;
  }

  inst_data->proc = mti_CreateProcess( "Test Process", checkValues,
                                      (void *)inst_data );
  mti_ScheduleWakeup( inst_data->proc, 6 );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( initInstance, 0 );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl;";
begin
end a;

library ieee;
use ieee.std_logic_1164.all;

entity top is

  type bitarray is array( 3 downto 0 ) of bit;

  type rectype is record
    a : bit;
    b : integer;
    c : bitarray;
  end record;

  type bigtime is range 0 to integer'high
    units
      hour;
      day   = 24 hour;
      week  = 7 day;
      month = 4 week;
      year  = 12 month;
    end units;

end top;

architecture a of top is

  signal bitsig      : bit       := '1';
  signal intsig      : integer   := 42;
  signal physsig     : bigtime   := 3 hour;
  signal realsig     : real      := 10.2;
  signal timesig     : time      := 3 ns;
  signal stdlogicsig : std_logic := 'H';

  signal stdlogicarr : std_logic_vector( 1 to 4 ) := "01LH";

  signal rec         : rectype   := ( '0', 0, "1001" );

  component for_model
  end component;

  for all : for_model use entity work.for_model(a);

begin

  inst1 : for_model;

  bitsig      <= not bitsig after 5 ns;
  intsig      <= intsig + 1 after 5 ns;
  physsig     <= physsig + 1 hour after 5 ns;
  realsig     <= realsig + 1.1 after 5 ns;
  timesig     <= timesig + 2 ns after 5 ns;
  stdlogicsig <= not stdlogicsig after 5 ns;

  stdlogicarr <= not stdlogicarr after 5 ns;

  rec.a       <= not rec.a after 5 ns;
  rec.b       <= rec.b + 1 after 5 ns;
  rec.c       <= not rec.c after 5 ns;

end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
VSIM 1> run 18
# Time [0,6]:
#   Signal bitsig = '0'
#   Signal intsig = 43
#   Signal physsig = 4 hour
#   Signal realsig = 11.3
#   Signal timesig = 5 ns
#   Signal stdlogicsig = '0'
#   Signal stdlogicarr = "1010"
#   Signal rec = {'1'} {1} {"0110"}
# Time [0,11]:
#   Signal bitsig = '1'
#   Signal intsig = 44
#   Signal physsig = 5 hour
#   Signal realsig = 12.4
#   Signal timesig = 7 ns
#   Signal stdlogicsig = '1'
#   Signal stdlogicarr = "0101"
#   Signal rec = {'0'} {2} {"1001"}
# Time [0,16]:
#   Signal bitsig = '0'
#   Signal intsig = 45
#   Signal physsig = 6 hour
#   Signal realsig = 13.5
#   Signal timesig = 9 ns
#   Signal stdlogicsig = '0'
#   Signal stdlogicarr = "1010"
#   Signal rec = {'1'} {3} {"0110"}
VSIM 2> quit 

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