mti_RemoveQuitCB()

Removes a simulator exit callback.

Syntax

mti_RemoveQuitCB( func, param ) 

Returns

Nothing

Arguments

Name	Type	Description
func	mtiVoidFuncPtrT	A pointer to a function being called at simulator exit
param	void *	The parameter that was specified in the call to mti_AddQuitCB() when the callback was created

Description

mti_RemoveQuitCB() removes the specified function from the simulator exit callback list. The param parameter must be the same parameter that was specified in the call to mti_AddQuitCB() when the callback was created.

Related functions

mti_AddQuitCB()

Example

FLI code

#include <stdlib.h>
#include <mti.h>

void quitCallback( void * param )
{
  if ( param ) {
    mti_PrintFormatted( "Cleaning up %s for simulator exit ...\n",
                       (char *)param );
    free( param );
  } else {
    mti_PrintFormatted( "Exiting simulator ...\n" );
  }
}

void loadDoneCallback( void * param )
{
  if ( (int)param == 1 ) {
    mti_RemoveQuitCB( quitCallback, 0 );
  }
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  char * instance_info;

  instance_info = malloc( strlen(param) + 1 );
  strcpy( instance_info, param );
  mti_AddQuitCB( quitCallback, instance_info );
  mti_AddQuitCB( quitCallback, 0 );
  if ( mti_IsFirstInit() ) {
    mti_AddLoadDoneCB( loadDoneCallback, 0 );
  } else {
    mti_AddLoadDoneCB( loadDoneCallback, 1 );
  }
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is
    "initForeign for_model.sl; for_model";
begin
end a;

entity top is
end top;

architecture a of top is

  signal s1 : bit := '0';

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

begin
  i1 : for_model;
  s1 <= not s1 after 5 ns;
end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
VSIM 1> run 20
VSIM 2> quit
# Exiting simulator ...
# Cleaning up for_model for simulator exit ...
% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
VSIM 1> run 20
VSIM 2> restart -f
# Loading ./for_model.sl
VSIM 3> run 10
VSIM 4> quit
# Cleaning up for_model for simulator exit ... 

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