mti_RemoveLoadDoneCB()

Removes an elaboration done callback.

Syntax

mti_RemoveLoadDoneCB( func, param ) 

Returns

Nothing

Arguments

Name	Type	Description
func	mtiVoidFuncPtrT	A pointer to a function being called at the end of elaboration
param	void *	The parameter that was specified in the call to mti_AddLoadDoneCB() when the callback was created

Description

mti_RemoveLoadDoneCB() removes the specified function from the end of elaboration callback list. The param parameter must be the same parameter that was specified in the call to mti_AddLoadDoneCB() when the callback was created.

mti_RemoveLoadDoneCB() must be called from a foreign initialization function in order for the callback removal to take effect. A foreign initialization function is specified either in the foreign attribute string of a foreign architecture or in the -foreign string option of a vsim command.

Related functions

mti_AddLoadDoneCB()

Example

FLI code

#include "mti.h"

void loadDoneCallback( void * param )
{
  mtiRegionIdT region = (mtiRegionIdT)param;

  mti_PrintFormatted( "Foreign Arch in Region %s: "
                     "the top-level region is %s.\n",
                     mti_GetRegionName( region ),
                     mti_GetRegionName( mti_GetTopRegion() ) );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( loadDoneCallback, region );
  if ( ! mti_IsFirstInit() ) {
    mti_RemoveLoadDoneCB( loadDoneCallback, region );
  }
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is
    "initForeign for_model.sl";
begin
end a;

entity bottom is
end bottom;

architecture b of bottom is
begin
end b;

entity top is
end top;

architecture a of top is

  signal s1 : bit := '0';

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

  component bottom is
  end component;

begin

  bot : bottom;

  i1 : for_model;

  s1 <= not s1 after 5 ns;

end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading work.bottom(b)
# Loading work.for_model(a)
# Loading ./for_model.sl
# Foreign Arch in Region i1: the top-level region is top.
VSIM 1> run 10
VSIM 2> restart -f 
# Loading ./for_model.sl
VSIM 3> run 10
VSIM 4> quit 

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