Pin - to Pin Delay

Pin - to - Pin delay, also called path delay, is delay assigned to paths from each input to each output. An example circuit is shown below.

Figure 3: Pin - to Pin delay

The total delay from each input to each output is given. The same example circuit as for the distributed and lumped delay model is used. This means that the sum delay from each input to each output is the same.

The module for the above circuit is shown beneath:

Module or_circ (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Blocks specified with path delay
specify
(a => out) = 7;
(b => out) = 7;
(c => out) = 9;
(d => out) = 9;
endspecify
//gate calculations
or a1(e, a, b);
or a2(f, c, d);
or a3(out, e, f);
endmodule

Path delays of a module are specified incide a specify block, as seen from the example above. An example of delay from the input, a, to the output, out, is written as (a => out) = delay, where delay sets the delay between the two ports. The gate calculations are done after the path delays are defined. Further information of path delay and specify blocks can be found through the following links:path delay and specify_blocks

For larger circuits, the pin - to - pin delay can be easier to model than distributed delay. This is because the designer writing delay models, needs to know only the input / output pins of the module, rather than the internals of the module. The path delays for digital circuits can be found through different simulation programs, for instance SPICE. Pin - to - Pin delays for standard parts can be found from data books. By using the path delay model, the program speed will increase.

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