A Module Path Delay can be defined as the delay between a source (input or inout) pin and destination (output or inout) pin on a module. A more detailed description of the Path Delay or pin-to-pin timing delay can be found in the Delay Description section.
There are two ways in which pin-to-pin delays can be expressed. A path delay can be constant for all possible conditions and independent from the rest of the circuit or it can depend on various internal or input conditions. Path Delays can therefore be either non-conditional or conditional. They must always be defined within a specify block, inside a module. A description of the syntax for defining non-conditional path delays is contained in the section on the Specify Block. In summary, the paths in a module can be defined as a number of Parallel Connections, each one specified using the => symbol, or as a set called a Full Connection, in which all paths implied using the *> symbol have an equal delay. For a module with many paths, a mix of Parallel and Full connections can be used to assign the various delays.
It is possible for the Path Delay within a module to change, depending on the inputs or internal states. Verilog allows Path Delays to be assigned CONDITIONALLY within the specify block used for defining Path delays. A conditional delay can be assigned using the if conditional statement. The syntax for the use of an if statement to assign path delays is shown:
Syntax: if (<conditional_expression>) <path> = <delay_value>;
The operands available for use in the conditional expression can be scalar or vector inputs, inout ports, registers and nets or part-selects.The operators used can be any bitwise, reduction, concatenation or conditional operator. The path description can contain both Parallel and Full connections. Verilog does not support the use of the else construct for use with the if statement for assigning Path Delays!
The following code demonstrates the use of the if statement to assign conditional path delays.
// Conditional Path Delay
module Mod_X(out, a, b, c);
output out;
input a, b, c;
wire d;
// Specify block assigning conditional path delays
specify
// Different path delay dependent on signal c state
if (c) (c => out) = 12;
if (~c) (c => out) = 8;
// Use of two operands
if (a | b) (a => out) = 10;
if (~(a | b)) (a => out) = 12;
// Conditional definition using Concatenation
if ({a,b} == 2'b11) (b => out) = 16;
if ({a,b} != 2'b11) (b => out) = 13;
endspecify
or o1 (d, a, b);
and a1 (out, d, c);
endmodule
The variety of different methods for assigning path delays can be seen from the use of the various operators and signal types. To avoid the possibility of a condition not being defined at least two if statements are used for each path, to cover all possibilities without the need for the else construct. This is done most efficiently by using an if statement to assign a delay to all the other cases not previously defined explicitly for each set of paths. Conditional Path Delays are also known as State Dependent Path Delays (SDPD).