Distributed Delay

Distributed delay is delay assigned to each gate in a module. An example circuit is shown below.

Figure 1: Distributed delay

As can be seen from Figure 1, each of the or-gates in the circuit above has a delay assigned to it:

When the input of any gate change, the output of the gate changes after the delay value specified.

The gate function and delay, for example for gate 1, can be described in the following manner:

or #4 a1 (e, a, b);

A delay of 4 is assigned to the or-gate. This means that the output of the gate, e, is delayed by 4 from the inputs a and b.

The module explaining Figure 1 can be of two forms:

1)
Module or_circ (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Delay distributed to each gate
or #4 a1 (e, a, b);
or #6 a2 (f, c, d);
or #3 a3 (out, e, f);
endmodule
2)
Module or_circ (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Delay distributed to each expression
assign #4 e = a & b;
assign #6 e = c & d;
assign #3 e = e & f;
endmodule

Version 1 models the circuit by assigning delay values to individual gates, while version 2 use delay values in individual assign statements. (An assign statement allows us to describe a combinational logic function without regard to its actual structural implementation. This means that the assign statement does not contain any modules with port connections.)

The above or_circ modules results in delays of (4+3) = 7 and (6+3) = 9 for the 4 connections part from the input to the output of the circuit.

contents next