4 Bit Ripple Carry Model

library ieee;

use ieee.std_logic_1164.all;

entity adder4bit is

   port ( a,b: in std_logic_vector(3 downto 0);

             cin : in std_logic;

             cout: out std_logic;

             sum: out std_logic_vector(3 downto 0)

  );

end adder4bit;

architecture bruteforce of adder4bit  is

-- temporary signals for internal carries

   signal  c : std_logic_vector(4 downto 0); .

begin

    process (a, b, cin, c)

    begin

      c(0) <= cin;

      -- full adder 0

      sum(0) <= a(0) xor b(0) xor c(0);

      c(1)      <= (a(0) and b(0)) or (c(0) and (a(0) or b(0)));

      -- full adder 1

      sum(1) <= a(1) xor b(1) xor c(1);

      c(2)      <= (a(1) and b(1)) or (c(1) and (a(1) or b(1)));

      -- full adder 2

      sum(2) <= a(2) xor b(2) xor c(2);

      c(3)      <= (a(2) and b(2)) or (c(2) and  (a(2) or b(2)));

      -- full adder 3

      sum(3) <= a(3) xor b(3) xor c(3);

      c(4)      <= (a(3) and b(3)) or (c(3) and  (a(3) or b(3)));

      cout      <= c(4);

end process;

end bruteforce;

Straight forward implementation. Nothing wrong with this.

However, is there an easier way?

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