4 Bit Ripple Carry Model using For Statement

signal c : std_logic_vector(4 downto 0); -- temporary signals for internal carries.

begin

process (a, b, cin, c)

begin

c(0) <= cin;

for i in 0 to 3 loop

-- all four full adders

sum(i) <= a(i) xor b(i) xor c(i);

c(i+1) <= (a(i) and b(i)) or (c(i) and (a(i) or b(i)));

end loop;

cout <= c(4);

end process;

end forloop;