Majority Gate with Temporary Signals

The following version of the majority gate uses some temporary signals (entity has been left out, is same).

-- the architecture now uses 4 concurrent statements

ARCHITECTURE  newconc of majority is

   signal t1, t2, t3 : std_logic ;

begin

  t1 <=  A and B;

  t2 <=  A and C;

  t3 <=  B and C;

  Y <=  t1 or t2 or t3;

end newconc;

Note that temporary signals are declared between architecture statement and begin statement.

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