Majority Gate with when-else statement

The following version of the majority gate uses a 'when-else' statement:

-- the architecture now uses a when-else statement.

ARCHITECTURE whenelse of majority is

begin

    Y <=  '1' when ( (A and B) or (A and C) or (B and C))

                  else '0';

end whenelse;

You will find that there are many different ways to accomplish the same result in VHDL.  There is usually no best way; just use one that you feel most comfortable with.

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