Majority Gate Example

The following is an example of a three input XOR gate (majority gate) implemented in VHDL

library ieee;

use ieee.std_logic_1164.all;

entity majority is

    port ( A, B, C : in std_logic;     -- two dashes is a COMMENT in VHDL

             Y: out std_logic

           );

end majority;

-- this is the architecture declaration, uses only one concurrent statement.

ARCHITECTURE concurrent of majority is

begin

Y <= (A and B) or (A and C) or (B and C);

end concurrent;

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