Simple VLSI processor

synthetisable description with COMPASS ASIC synthetiser

prepared by P. Bakowski

The processor specifications are given in lesson seven. The synthetisable version uses 16-bit words instead of 32-bit words as given in the specification.

Note that processor integrates no memory blocks. Consequently no synthethic components are necessary to synthetize the processor circuits.

More complex DSP processor with integrated synthetic components is presented in the next example.

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

LIBRARY COMPASS_LIB;

USE COMPASS_LIB.COMPASS.ALL;

entity proc_syn is

port(nreset: in bit; clk : in bit; at : out bit_vector(15 downto 0); dt : inout bit_vector(15 downto 0) );

end proc_syn;

architecture beh of proc_syn is

constant ZERO : bit_vector(15 downto 0):="0000000000000000";

constant ONE : bit_vector(15 downto 0):="0000000000000001";

-- programmer accessible registers

signal a,x,p: bit_vector(15 downto 0);

signal c: bit;

-- internal carriers

signal ir,ad: bit_vector(15 downto 0);

signal tir: bit_vector(15 downto 0);

begin

main:process(nreset,clk) -- sequential process

-- adduressing mode field

constant DIRECT: bit_vector(1 downto 0) :="00";

constant INDEXED: bit_vector(1 downto 0) :="01";

constant REL_FORW: bit_vector(1 downto 0) :="10";

constant REL_BACK: bit_vector(1 downto 0) :="11";

-- operation mode field

constant ADA: bit_vector(5 downto 0) :="011111"; -- integer:=31; -- 16#1F#

constant ANA: bit_vector(5 downto 0) :="011000"; -- integer:=24; -- 16#18#

constant LDA: bit_vector(5 downto 0) :="001111"; -- integer:=15; -- 16#0F#

constant STA: bit_vector(5 downto 0) :="000110"; -- integer:=6 ; -- 16#06#

constant LDX: bit_vector(5 downto 0) :="001100"; -- integer:=12; -- 16#0D#

constant INX: bit_vector(5 downto 0) :="101110"; -- integer:=46; -- 16#2E#

constant BCC: bit_vector(5 downto 0) :="110100"; -- integer:=52; -- 16#34#

constant B: bit_vector(5 downto 0) :="110101"; -- integer:=53; -- 16#35#

-- FSM states : processor sequencer is based on 4 states

type ETAT is (SN,S0,S1,S2);

variable e: ETAT; -- temporary variables

variable at_tmp: bit_vector(16 downto 0);

variable ad_tmp: bit_vector(15 downto 0);

variable irop: bit_vector(5 downto 0);

variable irad: bit_vector(1 downto 0);

variable tcon: integer;

begin

if(nreset='0') then -- initialize state

e:=SN; a<=ZERO;

at_tmp:=ZERO&'0'; at<=ZERO;

dt<=ZERO; ad_tmp:=ZERO;

x<=ZERO; c<='0'; p<=ZERO;

ir<=ZERO; tir<=ZERO; ad<=ZERO;

irad:="00";irop:="000000";

elsif clk'event and clk='1' then

case e is

when SN => p<=ZERO; e:=S0;

when S0 => ad_tmp:=p; ad<=ad_tmp ; ir<=dt ; p<=p+ONE ; e:=S1;

when S1 => irad:=ir(9 downto 8);

case irad is

when DIRECT => ad<="00000000"&ir(7 downto 0); e:=S2;

when INDEXED => tir<="00000000"&ir(7 downto 0); ad<=x+tir; e:=S2;

when REL_FORW => tir<="00000000"&ir(7 downto 0); ad<=(p+tir)+ONE; e:=S2;

when REL_BACK => tir<="00000000"&ir(7 downto 0); ad<=(p-tir)+ONE; e:=S2;

when others => assert(e=S1) -- assert false -- assert is ignored by synthesis tool

report "illegal instruction mode"

severity warning;

e:=SN;

end case;

when S2 => irop:=ir(15 downto 10);

case irop is

when ADA => at_tmp(15 downto 0):= a+dt; a<= at_tmp(15 downto 0); at<= at_tmp(15 downto 0); e:=S0;

when LDA => a<= a and dt ; e:=S0;

when STA => dt<= a ; e:=S0; when LDX => x<= dt ; e:=S0;

when INX => x<= x+ONE ; e:=S0;

when BCC => if c='1' then p<= ad ; end if; e:=S0;

when B => p<= ad ; e:=S0;

when others => assert (e=S0) -- assert false

report "illegal instruction code"

severity warning;

e:=SN;

end case;

end case;

end if;

end process main;

end beh;

back to synthesis lesson