Lesson seven

Second example : RAM plus processor

prepared by P. Bakowski

Introduction

This example is provided to show how to build packages containing necessary types and functions from a high level specification given in C language. The example illustrates how to approach complex algorithms and describe them in VHDL. Finally, we present how to build a simple system from the created RAM and processor components (entities).

Contents: specification , C-code, requirements, development, package, package body, RAM component, processor component, system

System "specification"

The system is built from two components: a RAM memory block and a simple processor module.

The processor specification (procedural specification) is given through a program written in C language. Note that this program contains many printing functions (e.g. printf()); these functions allow to trace the program execution and to monitor the content of processor registers.

The processor itself operates in three steps:

instruction fetch
address decode and calculate
execute step

The instruction format looks as follows:

|----|----|-------------------------|

31 ..27...23........................0

the field (31-28) contains the address code: ad_code
the field (27-24) contains the operation code: op_code
the field (23-0) contains the address offset

C - code of the micro-processor algorithm

#include "pb_1.h" /* this function prints 32-bit binary values */
#define RAM_SIZE 1024
#define NI 32
unsigned ad=0,pc=0,ir=0;
/* ad - address register, pc - program counter, ir - instruction register */
unsigned a=0, x=0, z=0;
/* a - accumulator, x - index register, z - zero flag */
unsigned ram[RAM_SIZE];
/* RAM memory block */
void addr_unit(ad_code)
/* this unit decodes and calculates the addresses */
unsigned ad_code;
{
}
void alu_unit(op_code) /* data xecution unit */
unsigned op_code;
{
}
fetch() /* first machine cycle */
{
ir=ram[pc];printf("ir=ram[pc]\n");
pc++;printf("pc++\n"); printf("ir :"); pb_1(ir); printf("pc :"); pb_1(pc);
}
decoder()
{
unsigned ad_code;
unsigned op_code;
ad_code=ir; ad_code>>=28;
addr_unit(ad_code); /* second machine cycle */
op_code=ir; op_code<<=4; op_code>>=28;
alu_unit(op_code); /* third machine cycle */
}
main()
{
int i;
ram[0]=0x03000001; ram[1]=0x04000000; ram[2]=0x05000000;
for(i=0;i<NI;i++)
{
fetch();
decoder();
}
}

Modeling requirements

The interconnection of the components requires the introduction of at least three-state logic including a high-impedance state - 'Z' and a bus resolution function. The use of arithmetic operation on bit_vectors with different sizes necessitates the use of a generic arithmetic function.
The presentation of the example starts with a simple TSL package for Three State Logic system developed in order to provide the required types and functions. The TSL package contains the declaration of a set of logic values (0,1,Z) and several data types necessary to construct bus resolution function BUSFUNC.
BUSFUNC displays a warning message if more then one active sources ('0' or '1') are detected.

Development

We start by the development of a package containing:

three-state to binary and binary to three-state conversion functions.
binary to integer conversion function - necessary to produce integer index from bit_vector address.
basic arithmetical functions to increment and to add the data-word and address values

We use the above package to design a small system with 2 components:

RAM memory entity : 32 words of 32 bits,
processor entity used to execute the program stored in RAM memory,
define three-state logic and the corresponding resolution function
define the type MOT et ADRESSE to the package.
define all necessary conversion functions: binary to three-state, three-state to binary, binary to integer,
define the required arithmetical operations on binary vectors (MOT)
simulate separately the described entities.
simulate the system.

Package `STSL`:

package STSL is

-- type bit_vector is array (natural range <> ) of bit;

type MVL is ('0','1','z');

type MVL_V is array (natural range <> ) of MVL;

subtype ADRESSE is bit_vector(31 downto 0);

subtype MOTB is bit_vector(31 downto 0);

function BUSFUNC (INPUT: MVL_V) return MVL;

function CONVERT(val: MOTB) return integer;

function increment (val : bit_vector) return bit_vector;

subtype TSL is BUSFUNC MVL;

type TSV is array (natural range <>) of TSL;

function mv2bit (val : TSV) return bit_vector;

function bit2mv (val : bit_vector) return TSV;

subtype MOT is TSV (31 downto 0) ;

function add2(addi1 : bit_vector; addi2 : bit_vector) return bit_vector;

function sou2(so1 : bit_vector; so2 : bit_vector) return bit_vector;

function et(et1 : bit_vector; et2 : bit_vector) return bit_vector;

end STSL;

package body STSL is

function BUSFUNC(input: MVL_V) return MVL is -- bus resolution function !!!

variable resolved_value: MVL:='z';

variable state:MVL:='z';

begin

for i in input'range loop

if input(i)/='z' then

resolved_value:= input(i);

assert state='z'

report "signal conflict in BUSFUNC"

severity warning; state:=input(i);

end if;

end loop;

return resolved_value;

end BUSFUNC;

function CONVERT (val : MOTB) return INTEGER is
variable result:INTEGER :=0;
begin

for i in val'low to val'high loop

if val(i)='1' then

result:=result + (2**i);

end if;

end loop;

return result;

end CONVERT;

function increment(val : bit_vector) return bit_vector is

alias input : bit_vector(val'length downto 1) is val;
variable result : bit_vector(input'range) := input;
variable carry : bit := '1';

begin

for i in input'low to input'high

loop
end loop;

return result;

end increment;

function mv2bit(val : TSV) return bit_vector is

variable result : bit_vector(val'range);

begin

for i in val'low to val'high loop

if val(i) = 'z' then result(i) := '0';

elsif val(i) = '0' then result(i) := '0';

else result(i) :='1';

end if;

end loop;

return result;

end mv2bit;

function bit2mv (val : bit_vector) return TSV is

variable result : TSV(val'range);

begin

for i in val'low to val'high loop

if val(i) = '0' then result(i) := '0';

else result(i) :='1';

end if;

end loop;

return result;

end bit2mv;

function add2 (addi1 : bit_vector; addi2 : bit_vector) return bit_vector is

variable somme : bit_vector(addi1'range) :=addi1;

variable carry : bit := '0';

begin

for i in addi1'low to addi1'high loop

somme(i) := ( addi1(i) and addi2(i) ) or (addi1(i) and carry ) or ( addi2(i) and carry);

carry := (carry and not addi1(i) and not addi2(i)) or (carry and addi1(i) and addi2(i)) or (not carry and addi1(i) and not addi2(i)) or (not carry and not addi1(i) and addi2(i) );

end loop;

return somme;

end add2;

function sou2 (so1 : bit_vector; so2 : bit_vector) return bit_vector is

variable diff : bit_vector(so1'range) := so1;

begin

for i in so1'low to so1'high loop

diff(i) := not so2(i);

end loop;

diff := increment(diff);

diff := add2(so1,diff);

return diff;

end sou2;

function et (et1 : bit_vector; et2: bit_vector) return bit_vector is

variable resultat : bit_vector(et1'range);

begin

for i in et1'low to et1'high loop

resultat(i) := et1(i) and et2(i);

end loop;

return resultat;

end et;

end STSL;

RAM memory entity

RAM block has two inputs:

ABUS: address bus - 32-bits wide
RW: read-write signal - when '0' write function is selected , when set to 'z', puts the outputs in high impedance state

and one input-output :

DBUS: data bus - 32-bit wide, set to high impedance when RAM block is not selected

use work.stsl.all;
entity RAM is

generic(tps : time := 5 ns);

port (abus : in MOTB; dbus : inout MOT; RW : in MVL);

end RAM;

architecture first of RAM is
begin
process(RW)
-- processus reexecute à chaque modif de RW

type MEM is array(0 to 31) of MOTB;

variable debut : bit := '1';

variable RAM : MEM;

begin

if debut = '1' then

RAM(0):="00000000000000000000000001000001";

RAM(1):="00000000000000000000000011000000";

RAM(2):="00000000000000000000000001001111";

RAM(3):="11111111001111110011110000010010";

RAM(4):="00111100100001000111111111100001";

RAM(5):="00011111111111111111100001000000";

RAM(6):="00110000000000000000011100100010";

RAM(7):="00000000000111111000000001000000";

debut := '0';

else

if RW /= 'z' then

if RW = '0' then

RAM(CONVERT(abus)) := mv2bit(dbus);

else

dbus <= bit2mv(RAM(CONVERT(abus))) after tps;

end if;

else

dbus <= "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz";

end if;

end process;

end first;

Micro-processor entity

one input : start
two outputs: RW and abus
one input-output: dbus

use work.stsl.all;
entity micro is
generic (tps : time := 10 ns);
port (abus : buffer MOTB; dbus : inout MOT; RW : out MVL; start : in bit);
-- on utilise buffer pour pouvoir modifier abus dans le programme
end micro;

architecture evaluation of micro is
type position is (fetch,decod,exec); -- permet de donner les differentes taches a executer au microprocesseur
signal possuiv : position := fetch;
-- tache suivante
signal a : MOTB :="00000000000000000000000000000000";
signal z : bit :='0';
begin
end evaluation;

System entity called `start`with one input signal: `top`

use work.stsl.all;
entity start is
port(top : in bit);
end start;
architecture structure of start is
component RAM
port(abus : in MOTB; dbus : inout MOT; RW : in MVL);
end component;
component Micro
port(abus : buffer MOTB; dbus : inout MOT; RW : out MVL; start : in bit);
end component;
signal adr : MOTB;
signal data : MOT := "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz";
signal EL : MVL;
begin
end structure;

Introduction

System "specification"

C - code of the micro-processor algorithm

Modeling requirements

Development

Package STSL:

RAM memory entity

Micro-processor entity

System entity called start with one input signal: top

Package `STSL`:

System entity called `start`with one input signal: `top`