prepared by P. Bakowski

The structural descriptions may be elaborated at any level of abstraction such as:

• logic level - gates and flip-flops
• register transfer level - registers, counters, ALUs, simple memory blocks
• processor-memory-switch level : processors, I/O interfaces, memory sub-systems

Note however that the components of higher abstraction levels may be decomposed into components of lower abstraction levels. For example a register block may be decomposed into several flip-flops and logic gates.

An assembly of register blocks, functional blocks like ALUs and decoders my be represented as structural description. In this case each memory or functional block is instantiated as separate component.

A digital electronic system is described in VHDL as a module with inputs and/or outputs. The electrical /logical values on the outputs are some function of the values on the inputs.

The above module MOD has tree inputs, a, b and cin , and two outputs s and cout. Using VHDL terminology, we call the module MOD a design entity , and the inputs and outputs are called ports .

One way of describing the function of a module is to describe how it is composed of sub-modules.

Each of the sub-modules is an instance of some entity, and the ports of the instances are connected using signals .

Logic level model

At this page we will first study a small example of a VHDL description of a full adder to give you an illustration of a simple structural description at logic level.

We start the description of an entity by specifying its external interface, which includes a description of its ports.

So the adder might be defined as:

-- single-bit adder

entity adder is

port (a,b,cin: in bit; sum,cout: out bit);

end adder;

This specifies the entity with 3 inputs and 2 outputs, all of which are bit values, that is, they can take on the only two values: `0' and `1'.

To understand the internal operations of the entity the folowing architecture is described functionally with two concurrent signal assignments.

-- description of adder using concurrent signal assignments

architecture rtl of adder is

begin

sum <= (a xor b) xor cin;

cout <= (a and b) or (cin and a) or (cin and b);

end rtl;

The entity may be enhanced with timing information using the generic statement which contains the predefined temporal parameters - delays:

-- single-bit adder

entity adder is

generic(sum_del:TIME:=10 ns; carry_del: TIME:= 15 ns);

port (a,b,cin: in bit; sum,cout: out bit);

end adder;

Which provides us with a reformulated architecture:

-- description of adder using concurrent signal assignments

architecture rtl of adder is

begin

sum <= (a xor b) xor cin after sum_del;

cout <= (a and b) or (cin and a) or (cin and b) after carry_del;

end rtl;

The next architecture is completely structural. It uses bgates library containing the description of gates like xorg, andg, and org.

These components are directly instantiated and interconnected through port map clause.

Note that the same component may be instantiated several times under different instantiation names.

The direct instantiation may be used only for the components/entities with single architecture.

To chose the components having more than one architecture one must use configuration clause.

-- description of adder using component direct instantiation statements

use work.bgates.all;

architecture structural of adder is

signal xor1_out, and1_out, and2_out, or1_out : bit;

begin

xor1: xorg port map(in1 => a,in2 => b, out1 => xor1_out);

xor2: xorg port map(in1 => xor1_out, in2 => cin,out1 => sum);

and1: andg port map(in1 => a,in2 => b,out1 => and1_out);

or1: org port map(in1 => a,in2 => b,out1 => or1_out);

and2: andg port map( in1 => cin, in2 => or1_out, out1 => and2_out);

or2: org port map(in1 => and1_out,in2 => and2_out, out1 => cout);

end structural;

RTL level model "specification"

The following example illustrates a simple two component system incorporating one memory block and one counter unit.

• The system is built from two components: a RAM memory block and an incrementer.
• The incrementer reads sequentially all memory words and increments them.
• The incrementation cycle is repeated ad infinitum.
• The incrementation is performed modulo 2 ^word_size.

Requirements

The interconnection of the components requires the introduction of at least three-state logic including a high-impedancy state - 'Z' and a bus resolution function.

The use of the incrementation operation on bit_vectors with different sizes necessitates the use of a generic increment function.

The example starts with a simple TSL package for Three State Logic system which needs to be developed in order to provide the required types and functions.

This package contains the declaration of a set of logic values (0,1,Z) and several data types necessary to construct bus resolution function BUSFUNC .

package STSL is type MVL is ('0','1','Z');

type MVL_V is array (NATURAL RANGE <> )of MVL;

function BUSFUNC(INPUT: MVL_V) return MVL; -- resolution function

subtype TSL is BUSFUNC MVL;

type TSV is array (NATURAL RANGE <>) of TSL;

end STSL;

package body STSL is

function BUSFUNC(input: MVL_V) return MVL is -- bus resolution function !!!

variable resolved_value: MVL:='Z';

variable state:MVL:='Z';

begin

for i in input'range loop

if input(i)/='Z' then

resolved_value:= input(i);

assert state='Z'

report "signal conflict in BUSFUNC"

severity warning; state:=input(i);

end if;

end loop;

return resolved_value;

end BUSFUNC;

end STSL;

Remark:

The BUSFUNC displays a message if more then one active signal sources ('0' or '1') are detected.

Development

Develop the above package adding three-state to binary and binary to three-state conversionfunctions.

Develop binary to integer conversion function - necessary to produce integer indexi from bit_vector address.

Use the above package to design a small system with 2 components:

• RAM memory entity : 16 words of 16 bits,
• incrementer entity used to increment the contents of all RAM memory words.
• add the type MOT et ADRESSE to the package.
• simulate separately the described entities.
• simulate the system.

Completed package STSL:

package STSL is

type MVL is ('0', '1', 'Z');

type MVL_V is array (NATURAL range<>) of MVL;

subtype MOT is BIT_VECTOR(15 downto 0);

subtype ADRESSE is BIT_VECTOR(3 downto 0);

function BUSFUNC(INPUT: MVL_V) return MVL;

function increment(val : BIT_VECTOR) return BIT_VECTOR;

function to_int(bv : bit_vector) return integer;

subtype TSL is BUSFUNC MVL;

type TSV is array(NATURAL range<>) of TSL;

subtype MOT_R is TSV(15 downto 0);

function to_bit(mr : MOT_R) return MOT;

function to_MVL(mv : MOT) return MOT_R;

end STSL;

package body STSL is

function BUSFUNC(input: MVL_V) return MVL is

variable resolved_value: MVL:='Z';

variable state: MVL := 'Z';

begin

for i in input'range loop

if input(i)/='Z' then

resolved_value:=input(i);

assert state='Z'

report "signal conflict in BUSFUNC"

severity warning;

state :=input(i);

end if;

end loop;

return resolved_value;

end BUSFUNC;

function increment(val : bit_vector) return bit_vector is

alias input : bit_vector(val'length downto 1) is val;

variable result : bit_vector(input'range) := input;

variable carry : bit := '1';

begin

for i in input'low to input'high

loop

result(i) := input(i) xor carry;

carry := input(i) and carry;

exit when carry = '0';

end loop;

return result;

end increment;

function to_int(bv : bit_vector) return integer is

variable result : integer := 0;

begin

for i in bv'range

loop

result := result * 2;

if (bv(i) = '1') then

result := result + 1;

end if;

end loop;

return result;

end to_int;

function to_bit(mr : MOT_R) return MOT is

variable m: MOT;

begin

for i in mr'range

loop

case mr(i) is

when '0' => m(i) :='0';

when '1' => m(i) :='1';

when 'Z' => m(i) :='0';

end case;

end loop;

return m;

end to_bit;

function to_mvl(mv : MOT) return MOT_R is

variable m: MOT_R:="ZZZZZZZZZZZZZZZZ";

begin

for i in mv'range

loop

case mv(i) is

when '0' => m(i) :='0';

when '1' => m(i) :='1';

end case;

end loop;

return m;

end to_mvl;

end STSL;

RAM memory entity has three inputs:

• ABUS: address bus - 4-bits wide
• SEL: selection signal - when is '0' the data bus output is set to high impedancy
• RW: read-write signal - when '0' write function is selected

and one input-output

• DBUS: data bus - 16-bit wide, set to high impedancy when RAM block is not selected

use work.STSL.all;

entity RAMBIS is

generic(RDEL, SDEL: time := 10 ns);

port (DBUS: inout MOT_R; ABUS : in ADRESSE; SEL,RW: in BIT);

end RAMBIS;

architecture SIMPLE of RAMBIS is

begin

process (SEL)

type MEMORY is array(0 to 15) of MOT;

variable MEM: MEMORY;

begin

if SEL ='1' then

if RW = '0' then

MEM(to_int(ABUS)) := to_bit(DBUS);

else

DBUS <= to_mvl(MEM(to_int(ABUS))) after RDEL;

end if;

else

DBUS <= "ZZZZZZZZZZZZZZZZ" after SDEL;

end if;

end process;

end SIMPLE;

incrementer entity has three outputs:

• ABUS: address bus - 4-bits wide
• SEL: selection signal - when is '0' the RAM block data bus output should be set to high impedancy
• RW: read-write signal - when '0' write function is required

one input:

• Go: starts the counting when set to '0'

and one input-output:

• DBUS: data bus - 16-bit wide

use work.STSL.all;

entity INCREMENTER is

port(dbus: inout MOT_R; abus: out add; RW: out bit;Go: in bit);

end INCREMENTER;

architecture SIMPLE of INCREMENTER is

begin

process

variable compteur: BIT_VECTOR(0 to 3) :="0000";

variable tampon: MOT;

begin

if go = '0' then

boucle1 :

loop

rw<='1';

abus<=compteur;

wait for 20 ns;

tampon:=to_bit(dbus);

tampon:=increment(tampon);

rw<='0';

dbus<=to_mvl(tampon);

compteur:=increment(compteur);

end loop;

end if;

end process;

end SIMPLE;

system entity has one input :

Go :activates the system-incrementer when set to '0'

use work.STSL.all;

entity SYSTEM is

port(Go : in bit; SEL : in bit);

end SYSTEM;

architecture STRUCTURE of SYSTEM is

component RAMBIS

port(DBUS: inout MOT_R; ABUS : in ADRESSE; SEL,RW: in BIT);

end component;

component INCREMENTER

port(dbus: inout MOT_R; abus: out ADRESSE; RW: out bit;Go: in bit);

end component;

signal donneebus : MOT_R := "ZZZZZZZZZZZZZZZZ";

signal adressebus : ADRESSE;

signal readwrite : bit;

-- there is no configuration section for the above components

-- only one architecture is provided for each component

begin

comp1 : RAMBIS

port map (DBUS=>donneebus, ABUS=>adressebus, SEL=>sel, RW=>readwrite);

comp2 : INCREMENTER

port map (DBUS=>donneebus, ABUS=>adressebus, RW=>readwrite, GO=>go);

end STRUCTURE;