prepared by P. Bakowski

A circuit is considered sequential if its outputs are a function not only of its inputs but also a function of a present state of the circuit. Sequential circuits feature internal memory keeping the state of the circuit.

We start our presentation of sequential circuit description by two simple examples: clock generator example and d-latch example. Then we illustrate how to describe the behaviour of more complex sequential circuits using the notion of state machines.

A simple clock generator

This page starts with a description of a simple clock:

The above circuit may be described as follows:

entity clock is

generic(period: TIME:= 15 ns);

port (clk: buffer bit); -- buffer declaration is required if clk is oused as I/O memory element

end clock;

architecture simple of clock is

begin

clk<= not clk after period/2;

end simple;

d-latch

The first latch example describes has only one input (d) and one output (q).

entity d_latch1 is

port(d: in bit; q:out bit);

end d_latch1;

architecture beh1 of d_latch1 is

begin

q <= d after delay; -- the output signal is maintained until the next event on d

end beh1;

The following is a more complete d-latch architecture featuring two aditional inputs : clk - synchronization and clr - reset

The following model uses block module.

entity d_latch2 is

port(d,clk,clr: in bit;q: out bit);

end d_latch2;

Clock level trigerred version:

architecture beh1 of d_latch2 is

begin

level_trigerred:

block(clk='1' or clr='1') -- level detection

begin

q <= guarded '0' when clr='1'; -- reset function

else d when clk='1'; -- clock level tested

else q; -- maintain function

end block level_trigerred;

end beh1;

Clock rising edge trigerred version:

architecture beh2 of d_latch2 is

begin

edge_trigerred:

block(clk='1' and not clk'stable or clr='1') -- rising edge detection

begin

q <= guarded '0' when clr='1'; -- reset function

else d when clk='1' and not clk'stable; -- clock rising edge tested

else q; -- maintains old value

end block edge_trigerred;

end beh2;

There are two styles to describe the state machine circuits in VHDL:

• as implicit finite state machine or
• as explicit finite state machine

The example of an implicit description uses a procedural flow control to determine the sequences of states. This flow is synchronized by the introduction of multiple wain until clock'event clauses.

The explicit representation of the states is restricted to the use of a single wait until clock'event clause.

The example describes the architecture of cross-road lights: green, yellow and red. In both descriptions the lights are in turn ON (red,yellow,green) unless there is a reset.

entity FSM is

port(reset,clk: in bit; red,yellow,green: out bit);

end FSM;

architecture implicit_arch of FSM is

begin

implicit_proc: process -- round robin process

-- the next state is indicated by the next wait

begin

wait until clk'event and clk='1';

if reset ='1' then

red <='0';

yellow <= '0';

green <= '0';

else

red <='1';

yellow <= '0';

green <= '0'

wait until clk'event and clk='1';

red <='0';

yellow <= '1';

green <= '0'

wait until clk'event and clk='1';

red <='0';

yellow <= '0';

green <= '1'

end if;

end process implicit_proc;

end implicit_arch;

The following is the explicit version of our FS machine. Note that at each clock event the model test the current state.

architecture explicit_arch of FSM is

type t_state is (rst,red_on,yellow_on,green_on);

signal etat : t_state; -- state register

begin

explicit_proc: process

begin

wait until clk'event and clk='1';

if reset ='1' then

etat <= rst;

red <='0';

yellow <= '0';

green <= '0';

elsif reset='0' and etat = rst then

etat <= red_on;

red <='1';

yellow <= '0';

green <= '0'

elsif etat = red_on then

etat <= yellow_on;

red <='0';

yellow <= '1';

green <= '0'

elsif etat = yellow_on then

etat <= green_on;

red <='0';

yellow <= '0';

green <= '1'

end if;

end process explicit_proc;

end explicit_arch;