prepared by P. Bakowski

VHDL entity declaration and generic values

The basic descriptional element of VHDL is entity; each description must be composed from at least one entity.

Each entity has a set of ports which constitute its interface to the outside world.

In VHDL, an entity is such a module which may be used as a component in a design, or which may be the top level module of the design.

Entity module may contain a generic statement which allows to characterize:

• the values for ranges (lower and upper limits): e.g loop upper limit
• the values characterizing the size of variables and signals: e.g. size of an array
• the values for timing parameters such as delays : e.g. value of inertial delay

The generic constants are default values; they may be instantiated from outside with new values.

Very simple examples:

Clock component with one generic parameter allowing to modify the clock frequency and

counter component with two generic parameters one allowing to determine the interval of counting (upper limit) and one allowing a possible modification .

entity horloge is

generic(period:time:= 50 ns); -- generic parameter period; with a by default value equal 50 ns

port(horl:out bit);

end horloge;

architecture simple of horloge is

signal temp: bit:=0;

begin

temp <= not temp after period/2;

horl <= temp;

end simple;

Counter component model:

entity mod_counter is

generic(retard: time:= 10 ns; modulus := 10);

port(rst, horl:in bit; c:out integer);

end mod_counter;

architecture simple of mod_counter is

signal tmp:= integer:=0;

begin

up_count: process(horl,rst)

begin

if rst='1' and rst'event then

tmp<= 0;

else

if horl='1' and horl'event then

tmp<= (tmp+1) mod modulus;

end if;

end if;

end process up_count;

c<= tmp after retard;

end simple;

Structural genericity : quantitative parameters

The following example shows the entity module which declares a RAM block component with address depth and data width dependent on generic constants.

This component can act as a template for a RAM entity .

component RAM_block

generic(depth:positive := 10; width:positive:=16) -- two generic values used to parametrise the size of RAM block

port(addr:in unsigned(depth-1 downto 0);

data:inout unsigned(width-1 downto 0);

sel,rw:in std_logic);

end component ;

The entity module corresponding to the above component may be described using a two-dimensional array with the indexes representing the depth and width of the array.

For example:

architecture simple of RAM_block is

subtype depth_t is integer range 0 to 2**depth-1;

subtype width_t is integer range width-1 downto 0;

subtype mem_word is unsigned(width_t);

type mem_t is array(depth_t) of mem_word;

begin

mem_p:

process(en,sel,rw)

variable memoire : mem_t := (others=>(others=>'0'));

begin

...

end process mem_p;

end simple;

Generic parameters instantiation

A component defined in an architecture may be instantiated using the syntax:

instantiation_label :

component_name

generic map ()

port_map()

...

This indicates that the architecture contains an instance of the named component, with actual values specified for generic constants, and with the component ports connected to actual signals or entity ports.

The RAM_block component declared in the above example may be instantiated twice as follows:

RAM_1:RAM_block

generic map(depth=>15,width=>7)

port map(addr=>baddr, data=>bdata, sel=>sel_1, rw=>srw);

RAM_2:RAM_block

generic map(depth=>15,width=>7)

port map(addr=>baddr, data=>bdata, sel=>sel_2, rw=>srw);

generic parameters and generate statement

As we have seen at the previous page the construction of of a complex circuit is long to prepare. For the cases, when the constructed circuit features a high degree of regularity , VHDL offers generate mechanism. Generate statement indicates the compiler how to multiply the instantiations of the components in order to build a regular structure.

The use of generate statement is illustrated below:

generate_label:

generation_scheme generate

concurrent statements

end generate generate_label;

The generation_scheme includes for loop with some internal conditions allowing to differentiate the instantiations:

for generate_parameter_specification | if condition

The following is an example of counter circuit generated from simple T-flip-flops and and gates. The width of the counter is a generic parameter which can be modified at the moment of component instantiation.

entity gen_counter is

generic(width:integer:=7);

port(clk, carry: in bit; dout: buffer bit_vector(width downto 0));

end gen_counter;

architecture str_gener of gen_counter is

component tff -- existing T-flip-flop component

port (clk: in bit; t: in bit; q:buffer bit);

end component;

component and2

port (i1,i2: in bit; o1: out bit);

end omponent;

signal s: bit_vector(width downto 0)

for all: tff use entity work.tff(simple);

for all: and2 use entity work.and2(and2);

begin

GEN: for i in width downto 0 generate

G1: if i=width generate

tff_width: tff port map(clk,s(i-1),dout(i));

end generate;

G2: if i=0 generate

tff_0: tff port map(clk,carry,dout(i));

s(i) <= dout(i);

end generate;

G3: if i<7 and i>0 generate

tff_1: tff port map(clk,s(i-1),dout(i));

and2_1: and2 port map(s(i-1),dout(i),s(i));

end generate;

end generate;

end str_gener;

Exercises