Register

One of the two Verilog data classes. Registers are used to store values in behavioural models.

{either}
reg [Range] RegisterOrMemory, ...;
integer RegisterOrMemory, ...;
time RegisterOrMemory, ...;
real RegisterName, ...;
realtime RegisterName, ...;

RegisterOrMemory = {either}
RegisterName
MemoryName [ConstantExpression:ConstantExpression]

Range = [ConstantExpression:ConstantExpression]

Where

See Declaration.

Rules

Registers may only be assigned from within initial or always statements.
In a given implementation, integers may have a maximum size, but it will be at least 32 bits. The length of a time reg is similarly guaranteed to be at least 64 bits.
A register of type integer or time behaves like a reg with the same number of bits. Individual bits and part selects of integers and times can be accessed in the same way as they can for regs.
Memory arrays may only be accessed (read or written) one whole element at a time. To access individual bits of an element in a memory array, the contents of the element must first be copied to an appropriate register.

Gotchas!

Whilst the name of this class of data types (register) implies a hardware register (i.e. a flip-flop), the name is supposed to indicate a software register (i.e. a variable). Verilog registers can be and are used to describe and synthesize both combinational logic, latches and flip-flops.
Type realtime is a recent addition to the Verilog language, and is not yet supported by all tools.

Synthesis

Real, time and realtime are not synthesizable.
In a combinational always block, registers are synthesized to wires, or, if incompletely assigned, to latches. In a clocked always block, registers are synthesized to wires or flip-flops, depending on the context.
An integer synthesizes to (at least) 32 bits. The value is represented as a binary number. Negative numbers are represented in two’s complement format.
Memory arrays will synthesize to flip-flops or wires, depending on the conext in which they are used. They do not synthesize to RAM or ROM components.

Tips

Use reg for describing logic, integer for loop variables and calculations, real in system models, and time and reatime for storing simulation times in test fixtures.

Example

reg a, b, c;
reg [7:0] mem[1:1024], byte;
real r;

The following fragment shows how the regs and integers are commonly used.

integer i;
reg [15:0] V;
reg Parity;

always @(V)
begin
  for ( i = 0; i <= 15; i = i + 1 )
  begin
    Parity = Parity ^ V[i];
  end
end