Key
to NotationKey
to NotationThe syntax definitions are written to look like examples whereever possible, but it has been necessary to introduce some extra notation. In brief, square brackets [] enclose optional items, three dots ... means repetition, and curly brackets {} enclose comments. ItalicNames represent parts of the syntax defined elsewhere.
Curly brackets {} enclose comments that are not part of the Verilog syntax being defined, but give you further information about the syntax definition. Bold curly brackets {} are part of the Verilog syntax (concatenation operator).
Syntax enclosed in square brackets [] is optional. Bold square brackets [] are part of the Verilog syntax (vector range, bit and part select, memory reference).
... means zero or more repetitions of the preceding item or line, or means a list, as follows:
Item ... means zero or more repetitions of the Item.
, ... means repeat in a comma separated list (e.g. A, B, C).
; ... means repeat in a semicolon separated list.
| ... means repeat in a bar separated list.
There must be at least one item in the list. There is no , or ; at the end of the list, unless it is given explicitly (as in ; ... ; ).
Words in lower case letters are reserved words, built into the Verilog language (e.g. module)
Capitalised Words (not in italics) are Verilog identifiers, i.e. user defined names that are not reserved identifiers (e.g. InstanceName).
Italic Words are syntactic categories, i.e. the name of a syntax definition given in full elsewhere. A syntactic category can be either defined on the same page, defined on a separate page, or the special category defined below.
Italics = indicates a syntactic category which is defined and used on the same page.
Special syntactic category:
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