Module

The module is the basic unit of hierarchy in Verilog. Modules contain declarations and functional decriptions and represent hardware components.

Syntax ( Key to Notation )

{either}

module ModuleName [(Port,...)];
  ModuleItem...
endmodule

macromodule ModuleName [(Port,...)];
  ModuleItem...
endmodule

ModuleItem = {either}
  Declaration
  Defparam
  Continuous Assignment
  Instance
  Specify
  Initial
  Always

Where

Modules are declared outside any other modules or primitives.

Rules

Several modules or primitives (or both) may be described in one file. (In fact, a single module can be spilt across two or more files, but this is not recommended.)
Modules may be defined instead as macromodules. The syntax is exactly the same as for modules, except for the keyword macromodule. A Verilog compiler may compile macromodules differently from modules, for example by not creating a level of hierarchy for a macromodule instance. In order to achieve this, macromodules may be subject to certain implementation specific restrictions. If these are not met, macromodules are treated as modules.

Gotchas!

The same keyword, endmodule, is used at the end of both modules and macromodules.

Synthesis

Each module is synthesized as a separate hierarchical block, allowing you to control the hierarchy of the synthesized netlist, although some tools flatten the hierarchy by default.
Not all tools support macromodules.

Tips

Have only one module declaration per file. This eases source code maintenance for a large design.

Example

macromodule nand2 (f, a, b);
  output f;
  input a, b;

  nand (f, a, b);
endmodule


module PYTHAGORAS (X, Y, Z);
  input  [63:0] X, Y;
  output [63:0] Z;

  parameter Epsilon = 1.0E-6;
  real RX, RY, X2Y2, A, B;

  always @(X or Y)
  begin
    RX = $bitstoreal(X);
    RY = $bitstoreal(Y);
    X2Y2 = (RX * RX) + (RY * RY);
    B = X2Y2;
    A = 0.0;
    while ((A - B) > Epsilon || (A - B) < -Epsilon)
    begin
      A = B;
      B = (A + X2Y2 / A) / 2.0;
    end
  end
  assign Z = $realtobits(A);
endmodule