Continuous Assignment

Either a concurrent statement (continuous assignment) or a statement (procedural continuous assignment).

A continuous assignment creates events on one or more nets whenever nets or registers in the expression on the right hand side of the continuous assignment change value.

A procedural continuous assignment, when active, similarly assigns values to one or more registers, and prevents ordinary procedural assignments from affecting the values of the assigned registers.

Syntax ( Key to Notation )

{Continuous assignment:}

assign [Strength] [Delay] NetTarget = Expression ;

NetTarget = {either}
  NetName
  NetName[ConstantExpression]
  NetName[ConstantExpression:ConstantExpression]
  {NetTarget,...}
(See also Net)
{Procedural continuous assignment:}

assign RegisterTarget = Expression ;
deassign RegisterTarget ;

RegisterTarget = {either}
  RegisterName
  RegisterName[Expression]
  RegisterName[ConstantExpression:ConstantExpression]
  MemoryName[Expression]
  {RegisterTarget,...}

Where

module-<HERE>-endmodule {Continuous assignment}

See Statement for procedural continuous assignment.

Rules

The nets in the target (left hand side) of a continuous assignment must have been declared explicitly in the source code before the continuous assignment statement.
After it is executed, a procedural continuous assignment remains in force on the target register(s) until it is deassigned, or until another procedural continuous assignment is made.
A force on a register overrides a continuous assignment on that register, until it is released, when the continuous assignment again takes effect.

Gotchas!

Continuous assignments are not the same as procedural continuous assignments, although they are similar. Make sure that you place an assign statement in the correct place: outside any initial or always statements for continuous assignments, and inside initial or always statements for procedural continuous assignments.

Synthesis

Delays and strengths are ignored by synthesis tools; use tool specific timing constraints instead.
Continuous assignments are synthesized as combinational logic.
Procedural continuous assignments are not synthesizable by all tools.

Tips

Use continuous assignments to describe combinational logic that can easily be described using a straightforward expression. Functions can be used to structure expressions. An always statement is usually better for describing more complex combinational logic, and may simulate more quickly than a number of separate continuous assignment statements.
Continuous assignments are useful for transfering register values to nets, when the Verilog syntax requires nets to be used. For example, to apply test stimulus described in an initial statement to an inout port of a module instance.
Procedural continuous assignments can be used to model asynchronous resets and interrupts

Example

wire cout, cin;
wire [31:0] sum, a, b;
assign {cout, sum} = a + b + cin;

wire enable;
wire [7:0] f;
reg [7:0] data;
assign #3 f = enable ? data : 8'bz;

always @(posedge Clock)
  Count = Count + 1;
always @(Reset)
  if (Reset)
    assign Count = 0;   // Prevents counting, until
                        // Reset goes low
  else
    deassign Count;